DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 968

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
ICCR1—I
ICCR0—I
Rev. 4.00 Jun 06, 2006 page 912 of 1004
REJ09B0301-0400
Note: * Only 0 can be written, to clear the flag.
I
2
Bit
Initial value
Read/Write
0
1
C bus interface enable
I
SCL and SDA signal pins set to port
function
Internal state initialization of I
interface module
SAR and SARX can be accessed
I
transfer operations (pins SCL and SCA
are driving the bus)
ICMR and ICDR can be accessed
2
2
C bus interface module disabled, with
C bus interface module enabled for
2
2
C Bus Control Register 1
C Bus Control Register 0
R/W
ICE
7
0
I
enable
2
0
1
C bus interface interrupt
IEIC
R/W
Interrupts disabled
Interrupts enabled
6
0
2
C bus
MST
R/W
5
0
Master/slave select (MST), transmit/receive select (TRS)
Note: For details, see section 16.2.5, I
TRS
R/W
0
1
4
0
0
1
0
1
Acknowledge bit judgement selection
Register (ICCR).
0
1
Slave receive mode
Slave transmit mode
Master receive mode
Master transmit mode
ACKE
Bus busy
The value of the acknowledge bit is ignored,
and continuous transfer is performed
If the acknowledge bit is 1, continuous
transfer is interrupted
H'FF88
H'FFD8
R/W
0
1
3
0
Bus is free
[Clearing condition]
When a stop condition is detected
Bus is busy
[Setting condition]
When a start condition is detected
Note: For the clearing and setting
I
2
0
1
C bus interface interrupt request flag
Start condition/stop condition
prohibit
0
1
Waiting for transfer, or transfer in
progress
Interrupt requested
BBSY
R/W
conditions, see section 16.2.5,
I
2
2
0
C Bus Control Register (ICCR).
Writing 0 issues a start or
stop condition, in combination
with the BBSY flag
Reading always returns a
value of 1; writing is ignored
R/(W) *
IRIC
1
0
2
C Bus Control
SCP
W
0
1
IIC1
IIC0