DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 663
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 21.14 shows the flash memory state transition diagram.
Legend:
RD: Memory read possible
VF: Verify-read possible
PR: Programming possible
ER: Erasing possible
Notes: 1. When an error occurs other than due to a SLEEP instruction, or when a SLEEP instruction is
Section 21 ROM
RD VF PR ER FLER = 0
2. When an error occurs due to a SLEEP instruction (except subactive mode)
3. Except sleep mode
4. VF in subactive mode
Program mode
occurrence *
Erase mode
RD VF *
executed for a transition to subactive mode
Error protection mode
Error
4
PR ER FLER = 1
1
(Mask ROM Version, H8S/2138 F-ZTAT, H8S/2134 F-ZTAT, and H8S/2132 F-ZTAT)
Figure 21.14 Flash Memory State Transitions
Error occurrence *
RD: Memory read not possible
VF: Verify-read not possible
PR: Programming not possible
ER: Erasing not possible
RES = 0 or STBY = 0
Software standby,
sleep, subsleep, and
watch mode
Software standby,
sleep, subsleep, and
watch mode release
2
RES = 0 or
STBY = 0
Rev. 4.00 Jun 06, 2006 page 607 of 1004
sleep, subsleep, and watch )
RES = 0 or
mode (software standby,
RD VF PR ER FLER = 1
STBY = 0
Error protection
Reset or hardware standby
RD VF PR ER FLER = 0
FLMCR1, FLMCR2 (except
FLER bit), EBR1, EBR2
initialization state *
(hardware protection)
REJ09B0301-0400
FLMCR1,
FLMCR2,
EBR1, EBR2
initialization
state
3
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