DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 546

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 I
[3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this
[4] Clear the IRIC flag to 0 to release from the wait state.
[5] When one frame of data has been transmitted, the IRIC and IRTR flags are set to 1 at the rise
[6] Read the ICDR receive data.
[7] Clear the IRIC flag to indicate the next wait.
[8] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed
[9] Clear the IRIC flag to 0 to release from the wait state. The master device outputs the 9th
[10] Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception.
[11] Clear the IRIC flag to release from the wait state.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
[13] Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear
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REJ09B0301-0400
point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
is cleared. If the first frame is the final reception frame, execute the end processing as
described in [10].
The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an
acknowledge signal.
of the 9th transmit clock pulse.
The master device continues to output the receive clock for the next receive data.
From clearing of the IRIC flag to completion of data reception as described in steps [5], [6],
and [7], must be performed within the time taken to transfer one byte because releasing of the
wait state as described in step [4] (or [9]).
low in synchronization with the internal clock until the IRIC flag is cleared. If this frame is
the final reception frame, execute the end processing as described in [10].
reception clock pulse, sets SDA to low, and returns an acknowledge signal.
By repeating steps [5] to [9] above, more data can be received.
Set the TRS bit of ICCR to 1 to change receive mode to transmit mode.
reception clock pulse.
the IRIC flag to 0.
Clear the IRIC flag only when WAIT = 0.
(If the stop-condition generation command is executed after clearing the IRIC flag to 0 and
2
C Bus Interface [H8S/2138 Group Option]