DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 23
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 23 of 1063
- Download datasheet (6Mb)
7.3
7.4
7.5
Section 8 I/O Ports
8.1
8.2
8.3
8.4
8.5
7.2.6
7.2.7
7.2.8
7.2.9
Operation .......................................................................................................................... 169
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
7.3.7
7.3.8
7.3.9
7.3.10 Number of DTC Execution States........................................................................ 182
7.3.11 Procedures for Using the DTC............................................................................. 184
7.3.12 Examples of Use of the DTC ............................................................................... 185
Interrupts ........................................................................................................................... 187
Usage Notes ...................................................................................................................... 187
Overview........................................................................................................................... 189
Port 1................................................................................................................................. 195
8.2.1
8.2.2
8.2.3
8.2.4
Port 2................................................................................................................................. 201
8.3.1
8.3.2
8.3.3
8.3.4
Port 3................................................................................................................................. 208
8.4.1
8.4.2
8.4.3
8.4.4
Port 4................................................................................................................................. 213
8.5.1
8.5.2
8.5.3
DTC Transfer Count Register B (CRB)............................................................... 166
DTC Enable Registers (DTCER) ......................................................................... 166
DTC Vector Register (DTVECR)........................................................................ 167
Module Stop Control Register (MSTPCR) .......................................................... 168
Overview.............................................................................................................. 169
Activation Sources ............................................................................................... 171
DTC Vector Table................................................................................................ 173
Location of Register Information in Address Space ............................................ 175
Normal Mode....................................................................................................... 176
Repeat Mode ........................................................................................................ 177
Block Transfer Mode ........................................................................................... 178
Chain Transfer ..................................................................................................... 180
Operation Timing................................................................................................. 181
Overview.............................................................................................................. 195
Register Configuration......................................................................................... 197
Pin Functions in Each Mode ................................................................................ 199
MOS Input Pull-Up Function............................................................................... 201
Overview.............................................................................................................. 201
Register Configuration......................................................................................... 203
Pin Functions in Each Mode ................................................................................ 205
MOS Input Pull-Up Function............................................................................... 207
Overview.............................................................................................................. 208
Register Configuration......................................................................................... 209
Pin Functions in Each Mode ................................................................................ 211
MOS Input Pull-Up Function............................................................................... 212
Overview.............................................................................................................. 213
Register Configuration......................................................................................... 213
Pin Functions ....................................................................................................... 214
.............................................................................................................. 189
Rev. 4.00 Jun 06, 2006 page xxi of liv
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