DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 567

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SCL
Internal clock
SDA
BBSY bit
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.18 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Notes on Start Condition Issuance for Retransmission
Figure 16.19 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After
retransmission start condition issuance is done and determined the start condition, write the
transmit data to ICDR, as shown below.
Figure 16.18 Points for Attention Concerning Reading of Master Receive Data
Master receive mode
Bit 0
8
A
9
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
ICDR reading
prohibited
Section 16 I
Confirmation of stop
condition generation
(0 read from BBSY)
Rev. 4.00 Jun 06, 2006 page 511 of 1004
Stop condition
2
C Bus Interface [H8S/2138 Group Option]
(a)
Start condition
issuance
REJ09B0301-0400
Start condition