DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 200

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 6 Bus Controller
Table 6.3
ABW
0
1
Note:
6.3.2
The H8S/2138 and H8S/2134 have 16 address output pins, so there are no pins for output of the
upper address bits (A16 to A23) in advanced mode. H'FFF000 to H'FFFE4F (H'FFF000 to
H'FFF7FF in the H8S/2138 F-ZTAT A mask version) can be accessed by designating the AS pin
as an I/O strobe pin. The accessible external space is therefore H'FFF000 to H'FFFE4F (H'FFF000
to H'FFF7FF in the H8S/2138 F-ZTAT A mask version) even when expanded mode with ROM
enabled is selected in advanced mode.
The initial state of the external space is basic bus interface, three-state access space. In ROM-
enabled expanded mode, the space excluding the on-chip ROM, on-chip RAM, and internal I/O
registers is external space. The on-chip RAM is enabled when the RAME bit in the system control
register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and
the corresponding space becomes external space.
6.3.3
The initial state of the external memory space is basic bus interface, three-state access space. In
ROM-disabled expanded mode, the space excluding the on-chip RAM and internal I/O registers is
external space. In ROM-enabled expanded mode, the space excluding the on-chip ROM, on-chip
RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME
bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-
chip RAM is disabled and the corresponding space becomes external space.
Rev. 4.00 Jun 06, 2006 page 144 of 1004
REJ09B0301-0400
* Except when WMS1 = 0 and WMS0 = 1
AST
0
0
1
Advanced Mode
Normal Mode
Bus Specifications for Each Area (Basic Bus Interface)
WMS1 WMS0 WC1
—
—
0
—*
—
—
1
—*
—
—
—
0
1
WC0
—
—
—
0
1
0
1
Bus Specifications (Basic Bus Interface)
Bus Width
Cannot be used in the H8S/2138 Group or
H8S/2134 Group.
8
8
Access
States
2
3
3
Program
Wait States
0
0
0
1
2
3