DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 134
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 134 of 1063
- Download datasheet (6Mb)
Section 3 MCU Operating Modes
3.3
3.3.1
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled.
Ports 1 and 2 function as an address bus, port 3 function as a data bus, and part of port 9 carries
bus control signals.
3.3.2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses. However, as these groups have a maximum of 16 address outputs, an external
address can be specified correctly only when the I/O strobe function of the AS/IOS pin is used.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals.
3.3.3
The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled.
After a reset, single-chip mode is set, and the EXPE bit in MDCR must be set to 1 in order to use
external addresses.
When the EXPE bit in MDCR is set to 1, ports 1 and 2 function as input ports after a reset. They
can be set to output addresses by setting the corresponding bits in the data direction register
(DDR) to 1. Port 3 function as a data bus, and part of port 9 carries bus control signals.
In products with an on-chip ROM capacity of 64 kbytes or more, the amount of on-chip ROM that
can be used is limited to 56 kbytes.
Rev. 4.00 Jun 06, 2006 page 78 of 1004
REJ09B0301-0400
Mode 1
Mode 2
Mode 3
Operating Mode Descriptions
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