DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 504

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 15 Serial Communication Interface (SCI, IrDA)
The high-level pulse width is fixed at a minimum of 1.41 µs, and a maximum of (3/16 + 2.5%)
bit rate or (3/16
minimum high-level pulse width at 1.41 µs or above.
When the serial data is 1, no pulse is output.
Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and
input to the SCI.
When a high-level pulse is detected, 0 data is output, and if there is no pulse during a one-bit
interval, 1 data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will
be identified as a 0 signal.
High-Level Pulse Width Selection: Table 15.12 shows possible settings for bits IrCKS2 to
IrCKS0 (minimum pulse width), and H8S/2138 Group and H8S/2134 Group operating frequencies
and bit rates, for making the pulse width shorter than 3/16 times the bit rate in transmission.
Rev. 4.00 Jun 06, 2006 page 448 of 1004
REJ09B0301-0400
Transmission
Bit
interval
Start
Start
bit rate) + 1.08 µs. When system clock is 20 MHz, 1.6 µs can be set as the
bit
bit
0
0
Figure 15.22 IrDA Transmit/Receive Operations
1
1
0
0
UART frame
IR frame
1
1
0
0
Data
Data
0
0
1
1
Reception
Pulse width is 1.6 µs
to 3/16 bit interval
1
1
0
0
Stop
Stop
bit
bit
1
1