DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 561

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.11 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR
register or clearing ICE bit. For details of CLR3 to CLR0 bits setting, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
The following items are not initialized:
Notes on Initialization:
TDRE and RDRF internal flags
Transmit/receive sequencer and internal operating clock counter
Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR)
Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, ICSR, and DDCSWR registers
The value of the ICMR register bit counter (BC2 to BC0)
Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
When initialization is executed by DDCSWR register, the write data for bits CLR3 to CLR0 is
not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to simultaneously
using an MOV instruction. Do not use a bit manipulation instruction such as BCLR. Similarly,
when clearing is required again, all the bits must be written to simultaneously in accordance
with the setting.
If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
Section 16 I
Rev. 4.00 Jun 06, 2006 page 505 of 1004
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C Bus Interface [H8S/2138 Group Option]
REJ09B0301-0400