DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 1000

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix B Internal I/O Registers
TCSR0—Timer Control/Status Register 0
Rev. 4.00 Jun 06, 2006 page 944 of 1004
REJ09B0301-0400
TCSR0
Bit
Initial value
Read/Write
Note:
* Only 0 can be written in bits 7 to 5, to clear the flags.
Compare match flag B
0
1
R/(W) *
CMFB
[Clearing conditions]
• Read CMFB when CMFB = 1, then write 0 in CMFB
• When the DTC is activated by a CMIB interrupt
[Setting condition]
When TCNT = TCORB
7
0
R/(W) *
CMFA
Compare match flag A
0
1
6
0
[Clearing conditions]
• Read CMFA when CMFA = 1, then write 0 in CMFA
• When the DTC is activated by a CMIA interrupt
[Setting condition]
When TCNT = TCORA
R/(W) *
OVF
Timer overflow flag
0
1
5
0
A/D trigger enable
[Clearing condition]
Read OVF when OVF = 1, then write 0 in OVF
[Setting condition]
When TCNT overflows from H'FF to H'00
0
1
A/D converter start requests by compare match A
are disabled
A/D converter start requests by compare match A
are enabled
Output select 3 and 2
ADTE
R/W
0
1
4
0
0
1
0
1
Output select 1 and 0
OS3
R/W
H'FFCA
0
1
0 output at compare match B
1 output at compare match B
Output inverted at compare
match B (toggle output)
3
0
No change at compare match B
0
1
0
1
OS2
R/W
No change at compare match A
0 output at compare match A
1 output at compare match A
Output inverted at compare
match A (toggle output)
2
0
OS1
R/W
1
0
OS0
R/W
0
0
TMR0