DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 555

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.3.8
The I
the slave address and the R/W bit, confirmation of reception with the acknowledge bit, indication
of the last frame, and so on. Therefore, continuous data transfer using the DTC must be carried out
in conjunction with CPU processing by means of interrupts.
Table 16.5 shows some examples of processing using the DTC. These examples assume that the
number of transfer data bytes is known in slave mode.
Table 16.5 Examples of Operation Using the DTC
Item
Slave address +
R/W bit
transmission/
reception
Dummy data
read
Actual data
transmission/
reception
Dummy data
(H'FF) write
Last frame
processing
Transfer request
processing after
last frame
processing
Setting of
number of DTC
transfer data
frames
2
C bus format provides for selection of the slave device and transfer direction by means of
Operation Using the DTC
Master Transmit
Mode
Transmission by
DTC (ICDR write)
—
Transmission by
DTC (ICDR write)
—
Not necessary
1st time: Clearing
by CPU
2nd time: End
condition issuance
by CPU
Transmission:
Actual data count
+ 1 (+1 equivalent
to slave address +
R/W bits)
Master Receive
Mode
Transmission by
CPU (ICDR write)
Processing by
CPU (ICDR read)
Reception by
DTC (ICDR read)
—
Reception by
CPU (ICDR read)
Not necessary
Reception: Actual
data count
Section 16 I
Rev. 4.00 Jun 06, 2006 page 499 of 1004
2
C Bus Interface [H8S/2138 Group Option]
Slave Transmit
Mode
Reception by
CPU (ICDR read)
—
Transmission by
DTC (ICDR write)
Processing by
DTC (ICDR write)
Not necessary
Automatic clearing
on detection of end
condition during
transmission of
dummy data (H'FF)
Transmission:
Actual data count
+ 1 (+1 equivalent
to dummy data
(H'FF))
Slave Receive
Mode
Reception by CPU
(ICDR read)
—
Reception by DTC
(ICDR read)
—
Reception by CPU
(ICDR read)
Not necessary
Reception: Actual
data count
REJ09B0301-0400