DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 590

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 17 Host Interface [H8S/2138 Group]
Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR2. This bit is an
internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads
IDR2.
The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For
details see table 17.8, Fast A20 Gate Output Signals.
Bit 1
IBF
0
1
Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR2. Cleared to
0 when the host processor reads ODR2. The IBF flag setting and clearing conditions are different
when the fast A20 gate is used. For details see table 17.8, Fast A20 Gate Output Signals.
Bit 0
OBF
0
1
Table 17.4 shows the conditions for setting and clearing the STR2 flags.
Rev. 4.00 Jun 06, 2006 page 534 of 1004
REJ09B0301-0400
Description
[Clearing condition]
When the slave processor reads IDR2
[Setting condition]
When the host processor writes to IDR2
Description
[Clearing condition]
When the host processor reads ODR2 or the slave writes 0 in the OBF bit
[Setting condition]
When the slave processor writes to ODR2
(Initial value)
(Initial value)