DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 239
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 239 of 1063
- Download datasheet (6Mb)
Table 7.9
The number of execution states is calculated from the formula below. Note that
of all transfers activated by one activation event (the number for which the CHNE bit is set to one,
plus 1).
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
Object of Access
Bus width
Access states
Execution
phase
Number of execution states = I · S
Number of States Required for Each Execution Phase
Vector read
Register
information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation
S
S
S
S
S
S
S
I
J
K
K
L
L
M
On-Chip
RAM
32
1
—
1
1
1
1
1
1
I
+
Section 7 Data Transfer Controller [H8S/2138 Group]
(J · S
On-Chip
ROM
16
1
1
—
1
1
1
1
1
J
+ K · S
Rev. 4.00 Jun 06, 2006 page 183 of 1004
K
+ L · S
Internal I/O
Registers
8
2
—
—
2
4
2
4
1
L
) + M · S
16
2
—
—
2
2
2
2
1
M
REJ09B0301-0400
External Devices
8
2
4
—
2
4
2
4
1
means the sum
8
3
6+2m
—
3+m
6+2m
3+m
6+2m
1
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