DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 973

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

SSR1—Serial Status Register 1
SSR2—Serial Status Register 2
SSR0—Serial Status Register 0
Bit
Initial value
Read/Write
Transmit data register empty
0 [Clearing conditions]
1 [Setting conditions]
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and writes data to TDR
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
R/(W) *
TDRE
7
1
R/(W) *
RDRF
Receive data register full
6
0
0 [Clearing conditions]
1 [Setting condition]
• When 0 is written in RDRF after reading RDRF = 1
• When the DTC is activated by an RXI interrupt and reads data from RDR
When serial reception ends normally and receive data is transferred from RSR to RDR
R/(W) *
ORER
Overrun error
0 [Clearing condition]
1 [Setting condition]
5
0
When the next serial reception is completed while RDRF = 1
When 0 is written in ORER after reading ORER = 1
Framing error
0 [Clearing condition]
1 [Setting condition]
When 0 is written in FER after reading FER = 1
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
R/(W) *
FER
4
0
Parity error
0 [Clearing condition]
1 [Setting condition]
When 0 is written in PER after reading PER = 1
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Rev. 4.00 Jun 06, 2006 page 917 of 1004
R/(W) *
Transmit end
H'FF8C
H'FFA4
H'FFDC
PER
0 [Clearing conditions]
1 [Setting conditions]
3
0
• When 0 is written in TDRE after reading TDRE = 1
• When the DTC is activated by a TXI interrupt and
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
writes data to TDR
a 1-byte serial transmit character
Appendix B Internal I/O Registers
Note: * Only 0 can be written, to clear the flag.
TEND
Multiprocessor bit
R
2
1
0 [Clearing condition]
1 [Setting condition]
When data with a 0 multiprocessor
bit is received
When data with a 1 multiprocessor
bit is received
Multiprocessor bit transfer
0 Data with a 0 multi-processor
1 Data with a 1 multi-processor
bit is transmitted
bit is transmitted
MPB
R
1
0
REJ09B0301-0400
MPBT
R/W
0
0
SCI1
SCI2
SCI0