DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 218

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 7 Data Transfer Controller [H8S/2138 Group]
7.2
7.2.1
MRA is an 8-bit register that controls the DTC operating mode.
Bits 7 and 6—Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is
to be incremented, decremented, or left fixed after a data transfer.
Bit 7
SM1
0
1
Bits 5 and 4—Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether
DAR is to be incremented, decremented, or left fixed after a data transfer.
Bit 5
DM1
0
1
Rev. 4.00 Jun 06, 2006 page 162 of 1004
REJ09B0301-0400
Bit
Initial value
Read/Write
DTC Mode Register A (MRA)
Register Descriptions
Bit 6
SM0
—
0
1
Bit 4
DM0
—
0
1
Unde-
SM1
fined
—
7
Description
SAR is fixed
SAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
SAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Description
DAR is fixed
DAR is incremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
DAR is decremented after a transfer
(by 1 when Sz = 0; by 2 when Sz = 1)
Unde-
fined
SM0
—
6
Unde-
DM1
fined
—
5
Unde-
DM0
fined
—
4
Unde-
MD1
fined
—
3
Unde-
MD0
fined
—
2
Unde-
fined
DTS
—
1
Unde-
fined
Sz
—
0