DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 484
![IC H8S/2100 MCU FLASH 80QFP](/photos/12/21/122132/df2134afa20v_sml.jpg)
DF2134AFA20V
Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets
1.HEWH8E10A.pdf
(19 pages)
2.D12312SVTE25V.pdf
(341 pages)
3.DF2134AFA20V.pdf
(1063 pages)
Specifications of DF2134AFA20V
Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 484 of 1063
- Download datasheet (6Mb)
Section 15 Serial Communication Interface (SCI, IrDA)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
2. The received data is stored in RSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
Rev. 4.00 Jun 06, 2006 page 428 of 1004
REJ09B0301-0400
synchronization and starts reception.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
b. Stop bit check:
c. Status check:
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error * is detected in the error check, the operation is as shown in table 15.11.
Note: * Subsequent receive operations cannot be performed when a receive error has
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must
be cleared to 0.
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