DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 21

• Manufacturer Part Number: DF2134AFA20V
• Description: IC H8S/2100 MCU FLASH 80QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8S/2100r

Specifications of DF2134AFA20V

• Core Processor: H8S/2000
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: IrDA, SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 58
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 80-QFP
• For Use With: 3DK2166 - DEV EVAL KIT H8S/2166
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 5 Interrupt Controller
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Section 6 Bus Controller
6.1
Overview........................................................................................................................... 101
5.1.1
5.1.2
5.1.3
5.1.4
Register Descriptions ........................................................................................................ 104
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.2.8
Interrupt Sources............................................................................................................... 113
5.3.1
5.3.2
5.3.3
Address Breaks ................................................................................................................. 118
5.4.1
5.4.2
5.4.3
5.4.4
Interrupt Operation............................................................................................................ 121
5.5.1
5.5.2
5.5.3
5.5.4
5.5.5
Usage Notes ...................................................................................................................... 132
5.6.1
5.6.2
5.6.3
DTC Activation by Interrupt............................................................................................. 134
5.7.1
5.7.2
5.7.3
Overview........................................................................................................................... 137
Features................................................................................................................ 101
Block Diagram ..................................................................................................... 102
Pin Configuration................................................................................................. 102
Register Configuration......................................................................................... 103
System Control Register (SYSCR) ...................................................................... 104
Interrupt Control Registers A to C (ICRA to ICRC)............................................ 105
IRQ Enable Register (IER) .................................................................................. 106
IRQ Sense Control Registers H and L (ISCRH, ISCRL)..................................... 106
IRQ Status Register (ISR).................................................................................... 107
Keyboard Matrix Interrupt Mask Register (KMIMR) ......................................... 109
Address Break Control Register (ABRKCR)....................................................... 111
Break Address Registers A, B, C (BARA, BARB, BARC)................................. 112
External Interrupts ............................................................................................... 113
Internal Interrupts................................................................................................. 115
Interrupt Exception Vector Table ........................................................................ 115
Features................................................................................................................ 118
Block Diagram ..................................................................................................... 118
Operation ............................................................................................................. 119
Usage Notes ......................................................................................................... 119
Interrupt Control Modes and Interrupt Operation ................................................ 121
Interrupt Control Mode 0 ..................................................................................... 124
Interrupt Control Mode 1 ..................................................................................... 126
Interrupt Exception Handling Sequence .............................................................. 129
Interrupt Response Times .................................................................................... 131
Contention between Interrupt Generation and Disabling..................................... 132
Instructions that Disable Interrupts ...................................................................... 133
Interrupts during Execution of EEPMOV Instruction.......................................... 133
Overview.............................................................................................................. 134
Block Diagram ..................................................................................................... 134
Operation ............................................................................................................. 135
................................................................................................... 137
.......................................................................................... 101
Rev. 4.00 Jun 06, 2006 page xix of liv