DF2134AFA20V Renesas Electronics America, DF2134AFA20V Datasheet - Page 733

IC H8S/2100 MCU FLASH 80QFP

DF2134AFA20V

Manufacturer Part Number
DF2134AFA20V
Description
IC H8S/2100 MCU FLASH 80QFP
Manufacturer
Renesas Electronics America
Series
H8® H8S/2100r
Datasheets

Specifications of DF2134AFA20V

Core Processor
H8S/2000
Core Size
16-Bit
Speed
20MHz
Connectivity
IrDA, SCI
Peripherals
POR, PWM, WDT
Number Of I /o
58
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
80-QFP
For Use With
3DK2166 - DEV EVAL KIT H8S/2166
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF2134AFA20V
Manufacturer:
Renesas Electronics America
Quantity:
10 000
23.4
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock ( ).
23.5
The medium-speed clock divider divides the system clock to generate /2, /4, /8, /16, and /32
clocks.
23.6
The bus master clock selection circuit selects the system clock ( ) or one of the medium-speed
clocks ( /2, /4, /8, /16, or /32) to be supplied to the bus master, according to the settings of
bits SCK2 to SCK0 in SBYCR.
23.7
The subclock input circuit controls the subclock input from the EXCL pin.
Inputting the Subclock: When a subclock is used, a 32.768-kHz external clock should be input
from the EXCL pin. In this case, clear bit P96DDR to 0 in P9DDR and set bit EXCLE to 1 in
LPWRCR.
The subclock input conditions are shown in table 23.6 and figure 23.8.
Table 23.6 Subclock Input Conditions
Item
Subclock input low
pulse width
Subclock input high
pulse width
Subclock input rise time
Subclock input fall time
Duty Adjustment Circuit
Medium-Speed Clock Divider
Bus Master Clock Selection Circuit
Subclock Input Circuit
Symbol
t
t
t
t
EXCLL
EXCLH
EXCLr
EXCLf
Min
V
CC
= 2.7 to 5.5 V
Typ
15.26
15.26
Rev. 4.00 Jun 06, 2006 page 677 of 1004
Max
10
10
Section 23 Clock Pulse Generator
Unit
µs
µs
ns
ns
Test Conditions
Figure 23.8
REJ09B0301-0400

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