UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 966

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

964
4th edition
Edition
Change of external bus interface in Table 19-1 Operating Statuses in HALT Mode
Change of Note in Figure 19-3 HALT Mode Release by Interrupt Request
Generation
Change of external bus interface in Table 19-2 Operating Statuses in STOP Mode
Change of Figure 19-5 Operation Timing When STOP Mode Is Released
(Release by Unmasked Interrupt Request)
Addition of Note to Figure 19-6 STOP Mode Release by Interrupt Request
Generation
Deletion of Note in 21.1 Functions of Power-on-Clear Circuit
Deletion of Note in 21.3 Operation of Power-on-Clear Circuit
Deletion of Note 6 in (1) When LVI is OFF upon power application (option byte:
LVIOFF = 1) in Figure 21-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
Deletion of Note 3 in (2) When LVI is ON upon power application (option byte:
LVIOFF = 0) in Figure 21-2 Timing of Generation of Internal Reset Signal by
Power-on-Clear Circuit and Low-Voltage Detector
Deletion of Note in 22.1 Functions of Low-Voltage Detector
Deletion of Note 2 in Figure 22-3 Format of Low-Voltage Detection Level Select
Register (LVIS)
Deletion of Note in 22.4 Operation of Low-Voltage Detector
Addition of description to 24.4 Setting of Option Byte
Addition of PG-FP5, FL-PR5, and QB-MINI2 as dedicated flash memory
programmers
Change of Figure 25-6 Format of Background Event Control Register (BECTL)
Change of Table 25-4 Communication Modes
Addition of 25.8 Processing Time of Each Command When Using PG-FP4 or PG-
FP5 (Reference Values)
Addition of Caution 5 to 25.9 Flash Memory Programming by Self-Programming
Change of description in 25.9.2 Flash shield window function
Change of Caution in 26.1 Connecting QB-MINI2 to 78K0R/KH3
Addition of Caution to Figure 26-1 Connection Example of QB-MINI2 and
78K0R/KH3
Change of Table 26-1 Differences Between 1-Line Mode and 2-Line Mode
Change of Table 28-1 Operand Identifiers and Specification Methods and change
of Remark
Change of description in 28.1.4 PREFIX instruction
Change of Remark 2 in Table 28-5 Operation List
Change of “Clocks” column of BTCLR instruction in Table 28-5 Operation List
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
CHAPTER 19
STANDBY FUNCTION
CHAPTER 21 POWER-
ON-CLEAR CIRCUIT
CHAPTER 22 LOW-
VOLTAGE DETECTOR
CHAPTER 24 OPTION
BYTE
CHAPTER 25 FLASH
MEMORY
CHAPTER 26 ON-
CHIP DEBUG
FUNCTION
CHAPTER 28
INSTRUCTION SET
Chapter
(12/13)