UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 324

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

322
Operation
start
During
operation
Operation
stop
TAU stop
Remark
Sets TOEmp (slave) to 1 (only when operation is
resumed).
The TSmn (master) and TSmp (slave) bits of the TSm
register are set to 1 at the same time.
Detects the TImn pin input valid edge of master channel.
Set values of only the CISmn1 and CISmn0 bits of the
TMRmn register can be changed.
Set values of the TMRmp, TDRmn, TDRmp registers,
TOMmn, TOMmp, TOLmn, and TOLmp bits cannot be
changed.
The TCRmn and TCRmp registers can always be read.
The TSRmn and TSRmp registers are not used.
Set values of the TOm and TOEm registers can be
changed.
The TTmn (master) and TTmp (slave) bits are set to 1 at
the same time.
TOEmp of slave channel is cleared to 0 and value is set
to the TOmp bit.
To hold the TOmp pin output levels
When holding the TOmp pin output levels is not
necessary
The TAU0EN bit, TAU1EN bit of the PER0 register is
cleared to 0.
Switches the port mode register to input mode.
The TTmn and TTmp bits automatically return to 0
because they are trigger bits.
m: Unit number, n: Channel number, p: Slave channel number (p = n+1),
When m = 0: n = 0, 2, 4, 6
When m = 1: n = 0, 2
The TSmn and TSmp bits automatically return to 0
because they are trigger bits.
Clears TOmp bit to 0 after the value to
be held is set to the port register.
Figure 7-66. Operation Procedure of One-Shot Pulse Output Function (2/2)
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
TEmn and TEmp are set to 1 and the master channel
enters the TImn input edge detection wait status.
Master channel starts counting.
Master channel loads the value of TDRmn to TCRmn
when the TImn pin valid input edge is detected, and the
counter starts counting down. When the count value
reaches TCRmn = 0000H, the INTTMmn output is
generated, and the counter stops until the next valid edge
is input to the TImn pin.
The slave channel, triggered by INTTMmn of the master
channel, loads the value of TDRmp to TCRmp, and the
counter starts counting down. The output level of TOmp
becomes active one count clock after generation of
INTTMmn from the master channel. It becomes inactive
when TCRmp = 0000H, and the counting operation is
stopped.
After that, the above operation is repeated.
TEmn, TEmp = 0, and count operation stops.
The TOmp pin outputs the TOmp set level.
The TOmp pin output levels is held by port function.
The TOmp pin output levels go are into Hi-Z output state.
Power-off status
Counter stops operating.
TCRmn and TCRmp hold count value and stops.
The TOmp output is not initialized but holds current
status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp bit is cleared to 0 and the TOmp pin is set to
port mode.)
Hardware Status