UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 375

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

11.3 Registers Used in A/D Converter
(1) Peripheral enable register 0 (PER0)
Address: F00F0H
The A/D converter uses the following seven registers.
• Peripheral enable register 0 (PER0)
• A/D converter mode register (ADM)
• A/D port configuration register (ADPC)
• Analog input channel specification register (ADS)
• Port mode registers 2 and 15 (PM2, PM15)
• 10-bit A/D conversion result register (ADCR)
• 8-bit A/D conversion result register (ADCRH)
Symbol
PER0
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the A/D converter is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution
ADCEN
RTCEN
<7>
0
1
After reset: 00H
When setting the A/D converter, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to a
control register of the A/D converter is ignored, and, even if the register is read, only the
default value is read (except for port mode registers 2 and 15 (PM2, PM15)).
Stops supply of input clock.
• SFR used by the A/D converter cannot be written.
• The A/D converter is in the reset status.
Supplies input clock.
• SFR used by the A/D converter can be read/written.
Figure 11-3. Format of Peripheral Enable Register 0 (PER0)
DACEN
<6>
R/W
ADCEN
CHAPTER 11 A/D CONVERTER
<5>
User’s Manual U18432EJ5V0UD
IIC0EN
Control of A/D converter input clock
<4>
SAU1EN
<3>
SAU0EN
<2>
TAU0EN
<1>
TAU0EN
<0>
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