UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 12

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 5 EXTERNAL BUS INTERFACE ...................................................................................... 180
CHAPTER 6 CLOCK GENERATOR .................................................................................................... 202
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4.3 Registers Controlling Port Function ........................................................................................ 163
4.4 Port Function Operations .......................................................................................................... 172
4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function........... 175
4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn).................................... 179
5.1 Functions of External Bus Interface......................................................................................... 180
5.2 Registers Controlling External Bus Interface Functions ....................................................... 185
5.3 Setting Port Mode Register and Output Latch ........................................................................ 188
5.4 Number of Instruction Wait Clocks or Data Access ............................................................... 189
5.5 Number of Instruction Execution Clocks and Instruction Wait Clocks for Fetch Access.. 189
5.6 Number of Instructed Wait Cycles According to External Wait Cycles................................ 190
5.7 Timing of External Bus Interface Function.............................................................................. 191
5.8 Example of Connection to Memory .......................................................................................... 200
6.1 Functions of Clock Generator................................................................................................... 202
6.2 Configuration of Clock Generator ............................................................................................ 203
6.3 Registers Controlling Clock Generator.................................................................................... 205
6.4 System Clock Oscillator ............................................................................................................ 219
6.5 Clock Generator Operation ....................................................................................................... 223
6.6 Controlling Clock........................................................................................................................ 227
4.2.15 Port 15...........................................................................................................................................161
4.2.16 Port 16...........................................................................................................................................162
4.4.1 Writing to I/O port ............................................................................................................................172
4.4.2 Reading from I/O port......................................................................................................................172
4.4.3 Operations on I/O port.....................................................................................................................172
4.4.4 Connecting to external device with different potential (2.5 V, 3 V) ..................................................173
5.7.1 Multiplexed bus mode .....................................................................................................................192
5.7.2 Separate bus mode .........................................................................................................................196
5.8.1 Connection of external logic (ASIC, etc.).........................................................................................200
5.8.2 Connection of synchronous memory ...............................................................................................200
5.8.3 Connection of asynchronous memory .............................................................................................201
6.4.1 X1 oscillator.....................................................................................................................................219
6.4.2 XT1 oscillator ..................................................................................................................................219
6.4.3 Internal high-speed oscillator ..........................................................................................................222
6.4.4 Internal low-speed oscillator............................................................................................................222
6.4.5 Prescaler .........................................................................................................................................222
6.6.1 Example of controlling high-speed system clock .............................................................................227
6.6.2 Example of controlling internal high-speed oscillation clock............................................................230
6.6.3 Example of controlling subsystem clock..........................................................................................232
6.6.4 Example of controlling internal low-speed oscillation clock .............................................................234
6.6.5 CPU clock status transition diagram................................................................................................235
6.6.6 Condition before changing CPU clock and processing after changing CPU clock ..........................240
6.6.7 Time required for switchover of CPU clock and main system clock ................................................242
6.6.8 Conditions before clock oscillation is stopped .................................................................................243
User’s Manual U18432EJ5V0UD