UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 946

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

944
Electrical
specifications
(standard
products)
Function
During
communication
at same potential
(CSI mode)
(slave mode,
SCKp... external
clock input)
During
communication
at same potential
(simplified I
mode)
During
communication
at different
potential (2.5 V,
3 V) (UART
mode)
(dedicated baud
rate generator
output)
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(master mode,
SCKp... internal
clock output)
During
communication
at different
potential (2.5 V,
3 V) (CSI mode)
(slave mode,
SCKp... external
clock input)
During
communication
at different
potential (2.5 V,
3 V) (simplified
I
2
C mode)
Details of
Function
2
C
Select the normal input buffer for SIj and SCKj and the normal output mode for SOj
by using the PIMg and POMg registers.
Select the normal input buffer and the N-ch open-drain output (V
for SDAr and the normal output mode for SCLr by using the PIMg and POMg
registers.
Select the TTL input buffer for RxDq and the N-ch open-drain output (V
Select the TTL input buffer for SIp and the N-ch open-drain output (V
mode for SOp and SCKp by using the PIMg and POMg registers.
Select the TTL input buffer for SIp and SCKp and the N-ch open-drain output (V
tolerance) mode for SOp by using the PIMg and POMg registers.
Select the TTL input buffer and the N-ch open-drain output (V
SDAr and the N-ch open-drain output (V
PIMg and POMg registers.
mode for TxDq by using the PIMg and POMg registers.
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
Cautions
DD
tolerance) mode for SCLr by using the
DD
tolerance) mode for
DD
tolerance) mode
DD
DD
tolerance)
tolerance)
DD
825, 827
to 830
p.820
p.823
pp.824,
pp.828
pp.832,
833
pp.834,
835
(32/35)
Page