UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 940

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

938
Power-on-
clear
circuit
Low-
voltage
detector
Function
Cautions for
power-on-clear
circuit
LVIM: Low-
voltage detection
register
LVIS: Low-
voltage detection
level select
register
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 1)
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 0)
Details of
Function
DD
DD
))
))
Input voltage from external input pin (EXLVI) must be EXLVI < V
In a system where the supply voltage (V
vicinity of the POC detection voltage (V
released from the reset status. In this case, the time from release of reset to the start
of the operation of the microcontroller can be arbitrarily set by taking the following
action.
To stop LVI, follow either of the procedures below.
• When using 8-bit memory manipulation instruction: Write 00H to LVIM.
• When using 1-bit memory manipulation instruction: Clear LVION to 0.
When LVI is used in interrupt mode (LVIMD = 0) and LVISEL is set to 0, an interrupt
request signal (INTLVI) that disables LVI operation (clears LVION) when the supply
voltage (V
voltage of external input pin (EXLVI) is less than or equal to the detection voltage
(V
Be sure to clear bits 4 to 7 to “0”.
Change the LVIS value with either of the following methods.
• When changing the value after stopping LVI
<1> Stop LVI (LVION = 0).
<2> Change the LVIS register.
<3> Set to the mode used as an interrupt (LVIMD = 0).
<4> Mask LVI interrupts (LVIMK = 1).
<5> Enable LVI operation (LVION = 1).
<6> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
• When changing the value after setting to the mode used as an interrupt (LVIMD =
<1> Mask LVI interrupts (LVIMK = 1).
<2> Set to the mode used as an interrupt (LVIMD = 0).
<3> Change the LVIS register.
<4> Before cancelling the LVI interrupt mask (LVIMK = 0), clear it with software
When an input voltage from the external input pin (EXLVI) is detected, the detection
voltage (V
<1> must always be executed.
immediately after the processing in <4>.
If supply voltage (V
reset signal is not generated.
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
0)
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
EXLVI
because an LVIIF flag may be set when LVI operation is enabled.
because an LVIIF flag may be set when the LVIS register is changed.
)) is generated and LVIIF may be set to 1.
APPENDIX B LIST OF CAUTIONS
EXLVI
DD
User’s Manual U18432EJ5V0UD
) is less than or equal to the detection voltage (V
) is fixed. Therefore, setting of LVIS is not necessary.
DD
) ≥ detection voltage (V
When LVIMK = 0, an interrupt may occur
Cautions
POC
), the system may be repeatedly reset and
DD
) fluctuates for a certain period in the
LVI
) when LVIMD is set to 1, an internal
LVI
) (if LVISEL = 1, input
DD
.
μ
s
p.708
p.713
p.713
p.713
p.714
p.715
p.715
p.717
p.717
p.719
(26/35)
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