UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 294

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Remark
292
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
1. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
2. f
Sets the TAU0EN bit, TAU1EN bit of the PER0 register to 1.
Sets the TPSm register.
Sets the TMRmn register (determines operation mode of
channel).
Sets the TISmn bit to 1 (f
the count clock.
Sets interval (period) value to the TDRmn register.
To use the TOmn output
Sets TOEmn to 1 (only when operation is resumed).
Sets the TSmn bit to 1.
Set values of the TMRmn register, TOMmn, and TOLmn
bits cannot be changed.
Set value of the TDRmn register can be changed.
The TCRmn register can always be read.
The TSRmn register is not used.
Set values of the TOm and TOEm registers can be
changed.
The TTmn bit is set to 1.
TOEmn is cleared to 0 and value is set to TOmn bit.
Figure 7-40. Operation Procedure of Interval Timer/Square Wave Output Function (1/2)
Determines clock frequencies of CKm0 and CKm1.
Clears the TOMmn bit of the TOMm register to 0
(toggle mode).
Clears the TOLmn bit to 0.
Sets the TOmn bit and determines default level of the
TOmn output.
Sets TOEmn to 1 and enables operation of TOmn.
Clears the port register and port mode register to 0.
The TSmn bit automatically returns to 0 because it is a
trigger bit.
The TTmn bit automatically returns to 0 because it is a
trigger bit.
mn = 00 to 07, 10 to 13
SUB
: Subsystem clock oscillation frequency
Software Operation
SUB
/4) when f
CHAPTER 7 TIMER ARRAY UNIT
SUB
User’s Manual U18432EJ5V0UD
/4 is selected as
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOmn pin goes into Hi-Z output state.
The TOmn default setting level is output when the port mode
register is in the output mode and the port register is 0.
TOmn does not change because channel stops operating.
The TOmn pin outputs the TOmn set level.
TEmn = 1, and count operation starts.
Counter (TCRmn) counts down. When count value reaches
0000H, the value of TDRmn is loaded to TCRmn again and
the count operation is continued. By detecting TCRmn =
0000H, INTTMmn is generated and TOmn performs toggle
operation.
After that, the above operation is repeated.
TEmn = 0, and count operation stops.
The TOmn pin outputs the TOmn set level.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDRmn is loaded to TCRmn at the count clock
input. INTTMmn is generated and TOmn performs toggle
operation if the MDmn0 bit of the TMRmn register is 1.
TCRmn holds count value and stops.
The TOmn output is not initialized but holds current status.
Hardware Status