UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 551
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UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Note1
SE
03
0
1
0
1
0
Table 13-8. Relationship between register settings and pins (Channel 3 of unit 0: CSI11, UART1 reception, IIC11)
032
MD
0
0
1
0
0
1
(Note and Remark are given on the next page.)
031
MD
0
1
0
0
1
0
SOE
03
0
0
1
1
0
1
1
0
0
1
1
1
0
SO03 CKO
Note4
Note4
Note4
Note4
Note7
Note4
Note4
Note4
Note8
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
1
1
1
1
Note4
Note4
Note4
Note4
Note7
Note4
Note4
Note8
0/1
0/1
0/1
0/1
0/1
0/1
0/1
0/1
03
1
1
1
1
1
TXE
03
0
0
1
1
0
1
1
0
0
1
0
1
1
0
0
RXE
03
0
1
0
1
1
0
1
1
0
0
1
0
0
1
0
Note3
Note3
PM
95
×
1
1
1
0
0
0
×
0
0
0
0
0
CHAPTER 13 SERIAL ARRAY UNIT
P95 PM96 P96 PM
Note3
Note3
×
×
×
×
1
1
1
×
1
1
1
1
1
User’s Manual U18432EJ5V0UD
Note3
Note3
Note3
Note3
×
1
×
1
1
×
1
×
0
0
0
0
0
Note3
Note3
Note3
Note3
×
×
×
×
×
×
×
×
1
1
1
1
1
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
97
×
×
0
0
×
0
0
×
×
×
×
×
×
P97 PM
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
×
×
1
1
×
1
1
×
×
×
×
×
×
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note2
03
×
×
×
×
×
×
×
1
×
×
×
×
×
P03
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note3
Note2
×
×
×
×
×
×
×
×
×
×
×
×
×
transmissi
Operation
Operation
transmission
transmission
/reception
transmission
transmission
/reception
reception
reception
reception
condition
transmissi
reception
condition
Notes 5, 6
UART1
address
Master
Master
Master
CSI11
CSI11
CSI11
CSI11
CSI11
CSI11
mode
mode
Slave
Slave
Slave
IIC11
IIC11
IIC11
IIC11
IIC11
start
stop
data
data
stop
field
on
on
(output)
(output)
(output)
SCK11/
SCL11/
SCK11
SCK11
SCK11
SCK11
SCK11
SCK11
SCL11
SCL11
SCL11
SCL11
SCL11
(input)
(input)
(input)
P95
P95
P95
SDA11/
SDA11
SDA11
SDA11
SDA11
SDA11
SI11/
SI11
SI11
SI11
SI11
P96
P96
P96
P96
P96
Pin Function
SO11/
SO11
SO11
SO11
SO11
P97
P97
P97
P97
P97
P97
P97
P97
P97
P97
P03
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
SDA10/
P03
P03
P03
P03
P03
P03
P03
P03
P03
P03
P03
P03
RxD1/
RxD1
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
SI00/
549
SI10/
P11
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
Note2
5/
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