UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 955

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

C.2 Revision History of Preceding Editions
2nd edition
Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition.
Edition
Deletion of target from the capacitance value of the capacitor connected to the
REGC pin
Change of corresponding pins of EV
Supplies
Change of description in 2.2.21 REGC
Change of description in 2.2.24 FLMD0
Modification of P60 to P64, P110 and P111 in Table 2-2. Connection of Unused
Pins
Modification of 12-D to 12-G, 37-A to 37-B, and 39 to 2-W in Table 2-2. Connection of
Unused Pins
Modification of 12-D to 12-G, 37-A to 37-B, and 39 to 2-W in Figure 2-1. Pin I/O
Circuit List
Change of address in Figure 3-16. Configuration of General-Purpose Registers
Addition of register and Note in Table 3-5. SFR List
Addition of the BCDADJ register to Table 3-6. Extended SFR (2
Change of address of the SOL0 register in Table 3-6. Extended SFR (2
(2/6)
Change of address and symbol of the SOL1 register in Table 3-6. Extended SFR
(2
Addition of PIM register and POM register in block diagram
Change of corresponding pins of EV
Supplies
Change of Cautions 1 and Cautions 2 in 4.2.1 Port 0
Change of Cautions 1, Cautions 2, and Cautions 3 in 4.2.2 Port 1
Change of Cautions 1 and addition of Cautions 2 in 4.2.4 Port 3
Change of Cautions 2 and Cautions 3 in 4.2.5 Port 4
Addition of Caution to 4.2.7 Port 6
Change of Caution in 4.2.10 Port 9
Change of Figure 4-36. Block Diagram of P110 and P111
Addition of description to 4.2.12 Port 12 and change of Cautions 2
Change of Caution in 4.2.13 Port 13
Change of Cautions 1 and Cautions 2 and addition of Cautions 3 to 4.2.14 Port 14
Change of Caution in 4.2.16 Port 16
Addition description to (4) Port input mode registers (PIM0, PIM4, PIM9, PIM12,
PIM14) and (5) Port output mode registers (POM0, POM4, POM9, POM12,
POM14) in 4.3
Change of Figure 4-56. Bit Manipulation Instruction (P10)
Addition of description to 5.1 Functions of External Bus Interface
Addition of description to title of (d) in Figure 5-5. Timing to Write to External
Memory
Change of (b) and (d) in Figure 5-6. Timing to Read External Memory
Addition of description to title of (c) in Figure 5-7. Timing to Write to External
Memory
nd
SFR) List (3/6)
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
DD
DD
Description
and V
and V
DD
DD
in Table 2-1. Pin I/O Buffer Power
in Table 4-1. Pin I/O Buffer Power
nd
SFR) List (1/6)
nd
SFR) List
Throughout
CHAPTER 2 PIN
FUNCTIONS
CHAPTER 3 CPU
ARCHITECTURE
CHAPTER 4 PORT
FUNCTIONS
CHAPTER 5
EXTERNAL BUS
INTERFACE
Chapter
(1/13)
953