UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 934

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

932
UART (UART0,
UART1,
UART2,
UART3)
communication
Simplified
I
IIC20)
communi-
cation
Serial
interface
IIC0
2
Function
C (IIC10,
UART
transmission (in
continuous
transmission
mode)
UART reception
Calculating baud
rate
Address field
transmission
Data reception
Calculating
transfer rate
IIC0: IIC shift
register 0
PER0:
Peripheral
enable register 0
IICC0: IIC
control register 0
IICF0: IIC flag
register 0
IICX0: IIC
function
expansion
register 0
Setting transfer
clock
Details of
Function
The MDmn0 bit can be rewritten even during operation.
However, rewrite it before transfer of the last bit is started, so that it has been
rewritten before the transfer end interrupt of the last transmit data.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
For the UART reception, be sure to set SMRmr of channel r that is to be paired with
channel n.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
Setting SDRmn [15:9] = (0000000B, 0000001B) is prohibited.
After setting the PER0 register to 1, be sure to set the SPSm register after 4 or more
clocks have elapsed.
completed by setting “1” to the STmn bit to stop operation and generating a stop
condition.
Setting SDRmn[15:9] = 0000000B is prohibited. Setting SDRmn[15:9] = 0000001B or
more.
Do not write data to IIC0 during data transfer.
Write or read IIC0 only during the wait period. Accessing IIC0 in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IIC0 can be written only once after the communication trigger bit
(STT0) is set to 1.
When setting serial interface IIC0, be sure to set IIC0EN to 1 first. If IIC0EN = 0,
writing to a control register of serial interface IIC0 is ignored, and, even if the register
is read, only the default value is read (except for port mode register 6 (PM6) and port
register 6 (P6)).
The start condition is detected immediately after I
while the SCL0 line is at high level and the SDA0 line is at low level. Immediately
after enabling I
manipulation instruction.
When bit 3 (TRC0) of IIC status register 0 (IICS0) is set to 1, WREL0 is set to 1
during the ninth clock and wait is canceled, after which TRC0 is cleared and the
SDA0 line is set to high impedance.
Write to STCEN only when the operation is stopped (IICE0 = 0).
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT0 = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE0 = 0).
Determine the transfer clock frequency of I
before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0)
to 1). To change the transfer clock frequency, clear IICE0 once to 0.
Determine the transfer clock frequency of I
before enabling the operation (by setting bit 7 (IICE0) of IIC control register 0 (IICC0)
to 1). To change the transfer clock frequency, clear IICE0 once to 0.
ACK is not output when the last data is received (NACK). Communication is then
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
2
C to operate (IICE0 = 1), set LREL0 (1) by using a 1-bit memory
Cautions
2
2
C by using CLX0, SMC0, CL01, and CL00
C by using CLX0, SMC0, CL01, and CL00
2
C is enabled to operate (IICE0 = 1)
p.506
p.507
pp.509,
510
pp.511,
514
p.523
p.531
p.540
p.542
p.558
p.561
p.562
p.565
p.569
p.569
p.571
p.577
p.558
p.569
(20/35)
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