UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 925

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Operation
of plural
channels
of timer
array unit
Real-time
counter
Function
HOUR: Hour
count register
WEEK: Week
count register
One-shot pulse
output function
Multiple PWM
output function
PER0:
Peripheral
enable register 0
RTCC0: Real-
time counter
control register 0
RTCC1: Real-
time counter
control register 1
RTCC2: Real-
time counter
control register 2
RSUBC: Sub-
count register
ALARMWM:
Alarm minute
register
Details of
Function
The timing of loading of TDRmn of the master channel is different from that of TDRmp
of the slave channel. If TDRmn and TDRmp are rewritten during operation, therefore,
an illegal waveform is output. Rewrite the TDRmn after INTTMmn is generated and
the TDRmp after INTTMmp is generated.
To rewrite both TDRmn of the master channel and TDRmp of the slave channel 1,
write access is necessary at least twice. Since the values of TDRmn and TDRmp are
loaded to TCRmn and TCRmp after INTTMmn is generated from the master channel,
if rewriting is performed separately before and after generation of INTTMmn from the
master channel, the TOmp pin cannot output the expected waveform. To rewrite both
TDRmn of the master and TDRmp of the slave, be sure to rewrite both the registers
immediately after INTTMmn is generated from the master channel (This applies also
to TDRmq of the slave channel 2) .
When using the real-time counter, first set RTCEN to 1, while oscillation of the
subsystem clock (f
time counter is ignored, and, even if the register is read, only the default value is read.
If RCLOE0 and RCLOE1 are changed when RTCE = 1, glitches may occur in the
32.768 kHz and 1 Hz output signals.
The RIFG and WAFG flags may be cleared when the RTCC1 register is written by
using a 1-bit manipulation instruction. Use, therefore, an 8-bit manipulation
instruction in order to write to the RTCC1 register. To prevent the RIFG and WAFG
flags from being cleared during writing, disable writing by setting “1” to the
corresponding bit. When the value may be rewritten because the RIFG and WAFG
flags are not being used, the RTCC1 register may be written by using a 1-bit
manipulation instruction.
Change ICT2, ICT1, and ICT0 when RINTE = 0.
When the output from RTCDIV pin is stopped, the output continues after a maximum
of two clocks of f
output is stopped immediately after entering the high level, a pulse of at least one
clock width of f
After the real-time counter starts operating, the output width of the RTCDIV pin may
be shorter than as set during the first interval period.
When a correction is made by using the SUBCUD register, the value may become
8000H or more.
This register is also cleared by reset effected by writing the second count register.
The value read from this register is not guaranteed if it is read during operation,
because a value that is changing is read.
Bit 5 (HOUR20) of HOUR indicates AM(0)/PM(1) if AMPM = 0 (if the 12-hour system
is selected).
The value corresponding to the month count register or the day count register is not
stored in the week count register automatically.
After reset release, set the week count register as follow.
Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the
range is set, the alarm is not detected.
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
XT
XT
may be generated.
SUB
and enters the low level. While 512 Hz is output, and when the
) is stable. If RTCEN = 0, writing to a control register of the real-
Cautions
p.339
p.316
p.323
p.334
p.335
p.337
p.338
p.338
p.338
p.339
p.339
p.340
p.343
p.346
923
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