UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 734

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UPD78F1174AGF-GAT-AX

Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1174AGF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
732
Figure 22-12. Delay from the time LVI reset source is generated until the time LVI reset has been generated or released
There is some delay from the time supply voltage (V
been generated.
In the same way, there is also some delay from the time LVI detection voltage (V
the time LVI reset has been released (see Figure 22-12).
Remark If bit 2 (LVISEL) of the low voltage detection register (LVIM) is set to “1”, the meanings of the above
See the timing in Figure 21-2 (2) When LVI is ON upon power application (option byte: LVIOFF = 0) for the
reset processing time until the normal operation is entered after the LVI reset is released.
<1> :
<2> :
Operation example 2: When used as interrupt
Supply voltage (V
<Action>
“supply voltage (V
of the LVI interrupt by using bit 0 (LVIF) of the low-voltage detection register (LVIM). Clear bit 1 (LVIIF) of
interrupt request flag register 0L (IF0L) to 0.
action after waiting for the supply voltage fluctuation time.
Confirm that “supply voltage (V
For a system with a long supply voltage fluctuation period near the LVI detection voltage, take the above
LVI reset signal
Minimum pulse width (200
Detection delay time (200
Interrupt requests may be generated frequently.
Take the following action.
words change as follows.
• Supply voltage (V
• Detection voltage (V
LVIF flag
V
DD
LVI
)
DD
) < detection voltage (V
DD
)
<1>
LVI
CHAPTER 22 LOW-VOLTAGE DETECTOR
μ
μ
) → Detection voltage (V
s (MAX.))
s (MIN.))
→ Input voltage from external input pin (EXLVI)
<2>
DD
) ≥ detection voltage (V
User’s Manual U18432EJ5V0UD
LVI
)” when detecting the rising edge of V
DD
) < LVI detection voltage (V
EXLVI
= 1.21 V)
LVI
)” when detecting the falling edge of V
<1>
<2>
LVI
LVI
Time
) ≤ supply voltage (V
) until the time LVI reset has
DD
, in the servicing routine
DD
DD
) until
, or

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