UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 915
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UPD78F1174AGF-GAT-AX
Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet
1.UPD78F1174AGF-GAT-AX.pdf
(968 pages)
Specifications of UPD78F1174AGF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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This appendix lists the cautions described in this document.
“Classification (hard/soft)” in the table is as follows.
Hard: Cautions for microcontroller internal/external hardware
Soft: Cautions for software such as register settings or programs
Outline
Pin
functions
Function
RTCCL, RTCDIV Do not enable outputting RTCCL and RTCDIV at the same time.
ANI0/P20 to
ANI7/P27
P40/TOOL0
ANI8/P150 to
ANI15/P157
AV
EV
EV
V
REGC
P20/ANI0 to
P27/ANI7,
P150/ANI8 to
P157/ANI15
P02/SO10/TxD1,
P04/SCK10/
SCL10
P10/SCK00/EX24,
P12/SO00/TxD0/
EX26
REGC
DD
SS
SS1
DD0
Details of
Function
, EV
, V
, EV
SS
SS0
DD1
,
,
Make AV
Make EV
Connect the REGC pin to V
P20/ANI0 to P27/ANI7 and P150/ANI8 to P157/ANI15 are set as analog inputs in the
order of P157/ANI15, …, P150/ANI8, P27/ANI7, …, P20/ANI0 by the A/D port
configuration register (ADPC). When using P20/ANI0 to P27/ANI7 and P150/ANI8 to
P157/ANI15 as analog inputs, start designing from P157/ANI15 (see 11.3 (6) A/D port
configuration register (ADPC) for details).
To use P02/SO10/TxD1 and P04/SCK10/SCL10 as general-purpose ports, set serial
communication operation setting register 02 (SCR02) to the default status (0087H).
In addition, clear port output mode register 0 (POM0) to 00H.
To use P10/SCK00/EX24 and P12/SO00/TxD0/EX26 as general-purpose ports, set
serial communication operation setting register 00 (SCR00) to the default status
(0087H).
ANI0/P20 to ANI7/P27 are set in the digital input (general-purpose port) mode after
release of reset.
The function of the P40/TOOL0 pin varies as described in (a) to (c) below.
In the case of (b) or (c), make the specified connection.
(a) In normal operation mode and when on-chip debugging is disabled (OCDENSET
(b) In normal operation mode and when on-chip debugging is enabled (OCDENSET
(c) When on-chip debug function is used, or in write mode of flash memory
ANI8/P150 to ANI15/P157 are set in the digital input (general-purpose port) mode
after release of reset.
Keep the wiring length as short as possible for the broken-line part in the above
figure.
APPENDIX B LIST OF CAUTIONS
= 0) by an option byte (000C3H)
= 1) by an option byte (000C3H)
programmer
=> Use this pin as a port pin (P40).
=> Connect this pin to EV
=> Use this pin as TOOL0.
high level to the pin before reset release.
emulator or a flash memory programmer, or pull it up by connecting it to
EV
SS
DD0
DD0
, EV
User’s Manual U18432EJ5V0UD
and EV
or EV
SS0
, and EV
DD1
DD1
the same potential as V
via an external resistor.
SS1
SS
the same potential as V
via a capacitor (0.47 to 1
DD0
or EV
Directly connect this pin to the on-chip debug
Cautions
DD1
via an external resistor, and always input a
DD
.
SS
.
μ
F).
p.22
p.22
p.22
p.22
p.37
p.38
p.38
p.38
p.40
p.46
p.48
913
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