UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 187

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.2 Registers Controlling External Bus Interface Functions
(1) Peripheral enable register 1 (PER1)
The external bus interface function is controlled by the following two registers.
• Peripheral enable register 1 (PER1)
• Memory extension mode control register (MEM)
• Port mode registers 0, 1, 5, 6, 7, 8, 9 (PM0, PM1, PM5, PM6, PM7, PM8, PM9)
• Port registers 0, 1, 5, 6, 7, 8, 9 (P0, P1, P5, P6, P7, P8, P9)
PER1 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro
that is not used is stopped in order to reduce the power consumption and noise.
When the external bus interface is used, be sure to set bit 0 (EXBEN) of this register to 1.
PER1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution When setting the external bus interface, be sure to set EXBEN to 1 first. If EXBEN = 0, writing to
Address: F00F1H
Symbol
PER1
a control register of the external bus interface is ignored, and, even if the register is read, only
the default value is read (except for port mode registers 0, 1, 5, 6, 7, 8, 9 (PM0, PM1, PM5, PM6,
PM7, PM8, PM9) and port registers 0, 1, 5, 6, 7, 8, 9 (P0, P1, P5, P6, P7, P8, P9)).
EXBEN
7
0
0
1
After reset: 00H
Figure 5-2. Format of Peripheral Enable Register 1 (PER1)
Stops supply of input clock.
• SFR used by external bus interface cannot be written.
• External bus interface is in the reset status.
Supplies input clock.
• SFR used by external bus interface can be read/written.
6
0
CHAPTER 5 EXTERNAL BUS INTERFACE
R/W
0
5
User’s Manual U18432EJ5V0UD
Control of external bus interface input clock
4
0
3
0
2
0
0
1
EXBEN
<0>
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