UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 332

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

330
During
operation
Operation
stop
TAU stop
Remark
The TTmn bit (master), TTmp, and TTmq (slave) bits are
set to 1 at the same time.
Set values of the TMRmn, TMRmp, TMRmq registers,
TOMmn, TOMmp, TOMmq, TOLmn, TOLmp, and TOLmq
bits cannot be changed.
Set values of the TDRmn, TDRmp, and TDRmq registers
can be changed after INTTMmn of the master channel is
generated.
The TCRmn, TCRmp, and TCRmq registers can always
be read.
The TSRmn, TSRmp, and TSRmq registers are not used.
Set values of the TOm and TOEm registers can be
changed.
TOEmp or TOEmq of slave channel is cleared to 0
and value is set to the TOmp and TOmq bits.
To hold the TOmp and TOmq pin output levels
When holding the TOmp and TOmq pin output levels is
not necessary
The TAU0EN bit, TAU1EN bit of the PER0 register is
cleared to 0.
Figure 7-71. Operation Procedure When Multiple PWM Output Function Is Used (2/2)
Clears TOmp and TOmq bits to 0 after
the value to be held is set to the port register.
Switches the port mode register to input mode.
The TTmn, TTmp, and TTmq bits automatically return
to 0 because they are trigger bits.
m: Unit number, n: Channel number, p: Slave channel number 1 (n+1), q: Slave channel number 2 (n+2)
When m = 0
When m = 1
n = 0, 2, 4
n < p < q ≤ 7 (where p and q are a consecutive integer greater than n)
n = 0
n < p < q ≤ 3 (where p and q are a consecutive integer greater than n ( p = 1, q = 2))
Software Operation
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
The counter of the master channel loads the TDRmn value
to TCRmn and counts down. When the count value
reaches TCRmn = 0000H, INTTMmn output is generated.
At the same time, the value of the TDRmn register is
loaded to TCRmn, and the counter starts counting down
again.
At the slave channel 1, the values of TDRmp are
transferred to TCRmp, triggered by INTTMmn of the master
channel, and the counter starts counting down. The output
levels of TOmp become active one count clock after
generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmp = 0000H, and
the counting operation is stopped.
At the slave channel 2, the values of TDRmq are
transferred to TDRmq, triggered by INTTMmn of the master
channel, and the counter starts counting down. The output
levels of TOmq become active one count clock after
generation of the INTTMmn output from the master
channel. It becomes inactive when TCRmq = 0000H, and
the counting operation is stopped.
After that, the above operation is repeated.
TEmn, TEmp and TEmq = 0, and count operation stops.
The TOmp and TOmq pins output the TOmp and TOmq
set levels.
The TOmp and TOmq pin output levels are held by port
function.
The TOmp and TOmq pin output levels go into Hi-Z output
state.
Power-off status
TCRmn, TCRmp and TCRmq hold count value and
stops.
The TOmp and TOmq output is not initialized but holds
current status.
All circuits are initialized and SFR of each channel is
also initialized.
(The TOmp and TOmq bits are cleared to 0 and the
TOmp and TOmq pins are set to port mode.)
Hardware Status