UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 217

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Caution Be sure to clear bits 1 to 7 of PER1 to 0.
SAU1EN
SAU0EN
TAU1EN
TAU0EN
EXBEN
0
1
0
1
0
1
0
1
0
1
Stops input clock supply.
• SFR used by the serial array unit 1 cannot be written.
• The serial array unit 1 is in the reset status.
Supplies input clock.
• SFR used by the serial array unit 1 can be read and written.
Stops input clock supply.
• SFR used by the serial array unit 0 cannot be written.
• The serial array unit 0 is in the reset status.
Supplies input clock.
• SFR used by the serial array unit 0 can be read and written.
Stops input clock supply.
• SFR used by the timer array unit 1 cannot be written.
• The timer array unit 1 is in the reset status.
Supplies input clock.
• SFR used by the timer array unit 1 can be read and written.
Stops input clock supply.
• SFR used by the timer array unit 0 cannot be written.
• The timer array unit 0 is in the reset status.
Supplies input clock.
• SFR used by the timer array unit 0 can be read and written.
Stops input clock supply.
• SFR used by the external bus interface cannot be written.
• The external bus interface is in the reset status.
Supplies input clock.
• SFR used by the external bus interface can be read and written.
Figure 6-7. Format of Peripheral Enable Register (2/2)
CHAPTER 6 CLOCK GENERATOR
User’s Manual U18432EJ5V0UD
Control of external bus interface input clock
Control of serial array unit 1 input clock
Control of serial array unit 0 input clock
Control of timer array unit 1 input clock
Control of timer array unit 0 input clock
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