UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 543

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.7.4 Stop condition generation
released.
After all data are transmitted to or received from the target slave, a stop condition is generated and the bus is
(1) Processing flow
SDAr output
SCLr output
Note During the receive operation, the SOEmn bit is set to 0 before receiving the last data.
Remark
SOEmn
SEmn
STmn
Note
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3), r: IIC number (r = 10, 11, 20, 21)
Figure 13-103. Timing Chart of Stop Condition Generation
Figure 13-104. Flowchart of Stop Condition Generation
Operation
stop
CHAPTER 13 SERIAL ARRAY UNIT
Writing 1 to STmn bit to clear
Starting generation of stop condition.
transmission/data reception
End of IIC communication
Writing 0 to SOEmn bit
Writing 1 to CKOmn bit
(SEmn is cleared to 0)
Writing 0 to SOmn bit
Writing 1 to SOmn bit
User’s Manual U18432EJ5V0UD
SOmn bit
manipulation
Completion of data
Wait
Stop condition
CKOmn bit
manipulation
SOmn bit
manipulation
Secure a wait time so that the specifications of
I
2
C on the slave side are satisfied.
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