UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 311

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.8 Operation of Plural Channels of Timer Array Unit
7.8.1 Operation as PWM function
(TSmn) is set to 1, INTTMmn is output.
synchronization with the count clock. When TCRmn = 0000H, INTTMmn is output. TCRmn loads the value of
TDRmn again. After that, it continues the similar operation.
the TOmp pin. TCRmp of the slave channel loads the value of TDRmp, using INTTMmn of the master channel as a
start trigger, and stops counting until the next start trigger (INTTMmn of the master channel) is input.
and inactive when TCRmp = 0000H.
Two channels can be used as a set to generate a pulse of any period and duty factor.
The period and duty factor of the output pulse can be calculated by the following expressions.
The master channel operates in the interval timer mode and counts the periods. When the channel start trigger
TCRmp of a slave channel operates in one-count mode, counts the duty factor, and outputs a PWM waveform from
The output level of TOmp becomes active one count clock after generation of INTTMmn from the master channel,
Caution To rewrite both TDRmn of the master channel and TDRmp of the slave channel, a write access is
Remark
Remark
Pulse period = {Set value of TDRmn (master) + 1} × Count clock period
Duty factor [%] = {Set value of TDRmp (slave)}/{Set value of TDRmn (master) + 1} × 100
0% output:
100% output: Set value of TDRmp (slave) ≥ {Set value of TDRmn (master) + 1}
When m = 0: n = 0, 2, 4, 6
When m = 1: n = 0, 2
necessary two times. The timing at which the values of TDRmn and TDRmp are loaded to TCRmn
and TRCmp is upon occurrence of INTTMmn of the master channel. Thus, when rewriting is
performed split before and after occurrence of INTTMmn of the master channel, the TOmp pin
cannot output the expected waveform. To rewrite both TDRmn of the master and TDRmp of the
slave, therefore, be sure to rewrite both the registers immediately after INTTMmn is generated
from the master channel.
m: Unit number, n: Channel number, p: Slave channel number (p = n+1)
The duty factor exceeds 100% if the set value of TDRmn (slave) > (set value of TDRmn (master) +
1), it summarizes to 100% output.
Set value of TDRmp (slave) = 0000H
CHAPTER 7 TIMER ARRAY UNIT
TCRmn counts down starting from the loaded value of TDRmn, in
User’s Manual U18432EJ5V0UD
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