UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 938

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

936
Key
interrupt
function
Standby
function
Function
KRM: Key return
mode register
OSTC:
Oscillation
stabilization time
counter status
register
OSTS:
Oscillation
stabilization time
select register
Details of
Function
−
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal high-
speed oscillation clock is being used as the CPU clock, set the oscillation stabilization
time as follows.
An interrupt will be generated if the target bit of the KRM register is set while a low
level is being input to the key interrupt input pin. To ignore this interrupt, set the
KRM register after disabling interrupt servicing by using the interrupt mask flag.
Afterward, clear the interrupt request flag and enable interrupt servicing after waiting
for the key interrupt input low-level width (250 ns or more).
The bits not used in the key interrupt mode can be used as normal ports.
The STOP mode can be used only when the CPU is operating on the main system
clock. The STOP mode cannot be set while the CPU operates with the subsystem
clock. The HALT mode can be used when the CPU is operating on either the main
system clock or the subsystem clock.
When shifting to the STOP mode, be sure to stop the peripheral hardware operation
operating with main system clock before executing STOP instruction.
The following sequence is recommended for operating current reduction of the A/D
converter when the standby function is used: First clear bit 7 (ADCS) and bit 0
(ADCE) of the A/D converter mode register (ADM) to 0 to stop the A/D conversion
operation, and then execute the STOP instruction.
It can be selected by the option byte whether the internal low-speed oscillator
continues oscillating or stops in the HALT or STOP mode.
CHAPTER 24 OPTION BYTE.
After the above time has elapsed, the bits are set to 1 in order from MOST8 and
remain 1.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
To set the STOP mode when the X1 clock is used as the CPU clock, set OSTS
before executing the STOP instruction.
Setting the oscillation stabilization time to 20
Before changing the setting of the OSTS register, confirm that the count operation of
the OSTC register is completed.
Do not change the value of the OSTS register during the X1 clock oscillation
stabilization time.
The oscillation stabilization time counter counts up to the oscillation stabilization time
set by OSTS. If the STOP mode is entered and then released while the internal
high-speed oscillation clock is being used as the CPU clock, set the oscillation
stabilization time as follows.
• Desired OSTC oscillation stabilization time ≤ Oscillation stabilization time set by
Note, therefore, that only the status up to the oscillation stabilization time set by
OSTS is set to OSTC after STOP mode is released.
The X1 clock oscillation stabilization wait time does not include the time until clock
oscillation starts (“a” below).
OSTS
OSTS
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
Cautions
μ
s or less is prohibited.
For details, see
p.679
p.679
p.680
p.680
p.680
p.680
p.681
p.681
p.681
p.682
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p.682
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