UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 415

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2 Configuration of Serial Array Unit
Serial array unit includes the following hardware.
Note The lower 8 bits of the serial data register mn (SDRmn) can be read or written as the following SFR,
Remark m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3),
Shift register
Buffer register
Serial clock I/O
Serial data input
Serial data output
Serial data I/O
Control registers
depending on the communication mode.
• CSIp communication … SIOp (CSIp data register)
• UARTq reception … RXDq (UARTq receive data register)
• UARTq transmission … TXDq (UARTq transmit data register)
• IICr communication … SIOr (IICr data register)
Item
p: CSI number (p = 00, 01, 10, 11, 20, 21), q: UART number (q = 0 to 3), r: IIC number (r = 10, 11, 20, 21)
8 bits
Lower 8 bits of serial data register mn (SDRmn)
SCK00, SCK01, SCK10, SCK11, SCK20, SCK21 pins (for 3-wire serial I/O), SCL10, SCL11,
SCL20, SCL21 pins (for simplified I
SI00, SI01, SI10, SI11, SI20, SI21 pins (for 3-wire serial I/O), R
UART), R
SO00, SO01, SO10, SO11, SO20, SO21 pins (for 3-wire serial I/O), T
UART), T
SDA10, SDA11, SDA20, SDA21 pins (for simplified I
<Registers of unit setting block>
• Peripheral enable register 0 (PER0)
• Serial clock select register m (SPSm)
• Serial channel enable status register m (SEm)
• Serial channel start register m (SSm)
• Serial channel stop register m (STm)
• Serial output enable register m (SOEm)
• Serial output register m (SOm)
• Serial output level register m (SOLm)
• Input switch control register (ISC)
• Noise filter enable register 0 (NFEN0)
<Registers of each channel>
• Serial data register mn (SDRmn)
• Serial mode register mn (SMRmn)
• Serial communication operation setting register mn (SCRmn)
• Serial status register mn (SSRmn)
• Serial flag clear trigger register mn (SIRmn)
• Port input mode registers 0, 4, 9, 12, 14 (PIM0, PIM4, PIM9, PIM12, PIM14)
• Port output mode registers 0, 4, 9, 12, 14 (POM0, POM4, POM9, POM12, POM14)
• Port mode registers 0, 1, 4, 9, 12, 14 (PM0, PM1, PM4, PM9, PM12, PM14)
• Port registers 0, 1, 4, 9, 12, 14 (P0, P1, P4, P9, P12, P14)
Table 13-1. Configuration of Serial Array Unit
X
X
D3 pin (for UART supporting LIN-bus), output controller
D3 pin (for UART supporting LIN-bus)
CHAPTER 13 SERIAL ARRAY UNIT
User’s Manual U18432EJ5V0UD
2
C)
Configuration
Note
2
C)
X
D0, R
X
X
D0, T
D1, R
X
X
D1, T
D2 pins (for
X
D2 pins (for
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