UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 702

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes 1.
700
Program counter (PC)
Stack pointer (SP)
Program status word (PSW)
RAM
Port registers (P0 to P9, P11 to P16) (output latches)
Port mode registers (PM0 to PM9, PM11 to PM16)
Port input mode registers 0, 4, 9, 12, 14 (PIM0, PIM4, PIM9, PIM12, PIM14)
Port output mode registers 0, 4, 9, 12, 14 (POM0, POM4, POM9, POM12, POM14)
Pull-up resistor option registers (PU0, PU1, PU3 to PU9, PU11 to PU14, PU16)
Memory extension mode control register (MEM)
Clock operation mode control register (CMC)
Clock operation status control register (CSC)
Processor mode control register (PMC)
System clock control register (CKC)
Oscillation stabilization time counter status register (OSTC)
Oscillation stabilization time select register (OSTS)
Noise filter enable registers 0, 1, 2 (NFEN0, NFEN1, NFEN2)
Peripheral enable registers 0, 1 (PER0, PER1)
Internal high-speed oscillator trimming register (HIOTRM)
Operation speed mode control register (OSMC)
Timer array unit
(TAU)
2.
During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
When a reset is executed in the standby mode, the pre-reset status is held even after reset.
Timer data registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TDR00,
TDR01, TDR02, TDR03, TDR04, TDR05, TDR06, TDR07, TDR10, TDR11,
TDR12, TDR13)
Timer mode registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TMR00,
TMR01, TMR02, TMR03, TMR04, TMR05, TMR06, TMR07, TMR10, TMR11,
TMR12, TMR13)
Timer status registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TSR00,
TSR01, TSR02, TSR03, TSR04, TSR05, TSR06, TSR07, TSR10, TSR11,
TSR12, TSR13)
Timer input select registers 0, 1 (TIS0, TIS1)
Timer counter registers 00, 01, 02, 03, 04, 05, 06, 07, 10, 11, 12, 13 (TCR00,
TCR01, TCR02, TCR03, TCR04, TCR05, TCR06, TCR07, TCR10, TCR11,
TCR12, TCR13)
Timer channel enable status registers 0, 1 (TE0, TE1)
Timer channel start registers 0, 1 (TS0, TS1)
Timer channel stop registers 0, 1 (TT0, TT1)
Timer clock select registers 0, 1 (TPS0, TPS1)
Timer output registers 0, 1 (TO0, TO1)
Timer output enable registers 0, 1 (TOE0, TOE1)
Timer output level registers 0, 1 (TOL0, TOL1)
Timer output mode registers 0, 1 (TOM0, TOM1)
Data memory
General-purpose registers
Table 20-2. Hardware Statuses After Reset Acknowledgment (1/3)
Hardware
CHAPTER 20 RESET FUNCTION
User’s Manual U18432EJ5V0UD
The contents of the
reset vector table
(0000H, 0001H) are set.
Undefined
06H
Undefined
Undefined
00H
FFH
00H
00H
00H
00H
00H
C0H
00H
09H
00H
07H
00H
00H
10H
00H
0000H
0000H
0000H
00H
FFFFH
0000H
0000H
0000H
0000H
0000H
0000H
0000H
0000H
Acknowledgment
After Reset
Note 2
Note 2
Note 1