UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 16

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

CHAPTER 14 SERIAL INTERFACE IIC0............................................................................................ 555
CHAPTER 15 MULTIPLIER................................................................................................................... 628
CHAPTER 16 DMA CONTROLLER ..................................................................................................... 631
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14.1 Functions of Serial Interface IIC0 ........................................................................................... 555
14.2 Configuration of Serial Interface IIC0 ..................................................................................... 558
14.3 Registers to Controlling Serial Interface IIC0........................................................................ 561
14.4 I
14.5 I
14.6 Timing Charts ........................................................................................................................... 621
15.1 Functions of Multiplier ............................................................................................................. 628
15.2 Configuration of Multiplier ...................................................................................................... 629
15.3 Operation of Multiplier ............................................................................................................. 630
16.1 Functions of DMA Controller .................................................................................................. 631
16.2 Configuration of DMA Controller ............................................................................................ 632
16.3 Registers to Controlling DMA Controller............................................................................... 635
16.4 Operation of DMA Controller................................................................................................... 638
16.5 Example of Setting of DMA Controller ................................................................................... 640
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14.4.1 Pin configuration ...........................................................................................................................573
14.5.1 Start conditions .............................................................................................................................574
14.5.2 Addresses .....................................................................................................................................575
14.5.3 Transfer direction specification......................................................................................................575
14.5.4 Transfer clock setting method .......................................................................................................576
14.5.5 Acknowledge (ACK) ......................................................................................................................577
14.5.6 Stop condition ...............................................................................................................................579
14.5.7 Wait ...............................................................................................................................................580
14.5.8 Canceling wait ...............................................................................................................................582
14.5.9 Interrupt request (INTIIC0) generation timing and wait control......................................................583
14.5.10 Address match detection method ................................................................................................584
14.5.11 Error detection.............................................................................................................................584
14.5.12 Extension code............................................................................................................................584
14.5.13 Arbitration....................................................................................................................................585
14.5.14 Wakeup function .........................................................................................................................586
14.5.15 Communication reservation.........................................................................................................587
14.5.16 Cautions ......................................................................................................................................591
14.5.17 Communication operations..........................................................................................................592
14.5.18 Timing of I
16.4.1 Operation procedure .....................................................................................................................638
16.4.2 Transfer mode...............................................................................................................................639
16.4.3 Termination of DMA transfer .........................................................................................................639
16.5.1 CSI consecutive transmission .......................................................................................................640
16.5.2 CSI master reception.....................................................................................................................642
16.5.3 CSI transmission/reception ...........................................................................................................644
16.5.4 Consecutive capturing of A/D conversion results ..........................................................................646
16.5.5 UART consecutive reception + ACK transmission ........................................................................648
C Bus Mode Functions .......................................................................................................... 573
C Bus Definitions and Control Methods .............................................................................. 574
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C interrupt request (INTIIC0) occurrence...................................................................600
User’s Manual U18432EJ5V0UD