UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 278

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.4 Channel Output (TOmn pin) Control
7.4.1 TOmn pin output circuit configuration
276
Interrupt signal of the master channel
Interrupt signal of the slave channel
The following describes the TOmn pin output circuit.
(Remark is given on the next page.)
<1> When TOMmn = 0 (toggle mode), the set value of the TOLmn register is ignored and only INTTMmp
<2> When TOMmn = 1 (combination-operation mode), both INTTMmn (master channel timer interrupt) and
<3> When TOEmn = 1, INTTMmn (master channel timer interrupt) and INTTMmp (slave channel timer
<4> When TOEmn = 0, writing to TOmn bit to the target channel (TOmn signal) becomes valid. When TOEmn
<5> The TOmn register can always be read, and the TOmn pin output level can be checked.
(slave channel timer interrupt) is transmitted to the TOmn register.
INTTMmp (slave channel timer interrupt) are transmitted to the TOmn register.
At this time, the TOLmn register becomes valid and the signals are controlled as follows:
When INTTMmn and INTTMmp are simultaneously generated, (0% output of PWM), INTTMmp (reset
signal) takes priority, and INTTMmn (set signal) is masked.
interrupt) are transmitted to the TOmn register.
becomes invalid.
When TOEmn = 1, the TOmn pin output never changes with signals other than interrupt signals.
To initialize the TOmn pin output level, it is necessary to set TOEmn = 0 and to write a value to TOmn.
= 0 neither INTTMmn (master channel timer interrupt) nor INTTMmp (slave channel timer interrupt) is
transmitted to TOmn register.
When TOLmn = 0: Forward operation (INTTMmn → set, INTTMmp → reset)
When TOLmn = 1: Reverse operation (INTTMmn → reset, INTTMmp → set)
(INTTMmn)
(INTTMmp)
Figure 7-26. Output Circuit Configuration
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
<1>
<2>
TOLmn
TOMmn
TOEmn
<3>
Writing to the TOmn register (TOmn write signal)
TOmn write signal
<4>
TOmn register
Set
Reset/toggle
<5>
Internal bus
TOmn pin