UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 818

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UPD78F1174AGF-GAT-AX

Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1174AGF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
(2) External bus interface (4/5)
816
CLKOUT cycle
RD low-level width
WR0, WR1 low-level width
Data input setup time to RD↑
Data input hold time from RD↑
Data output setup time to WR0, WR1↓
Data output hold time from WR0, WR1↑
Delay time from RD↓ to address
Address setup time to WR0, WR1↓
CLKOUT cycle
RD low-level width
WR0, WR1 low-level width
Data input setup time to RD↑
Data input hold time from RD↑
Data output setup time to WR0, WR1↓
Data output hold time from WR0, WR1↑
Delay time from RD↓ to address
Address setup time to WR0, WR1↓
Cautions 1. CLKOUT output is not used during CLKOUT asynchronous operation, but a CPU wait occurs
Remarks 1. f
(b) Read/write cycle (CLKOUT asynchronous)
• Conventional-specification products (
• Expanded-specification products (
(T
(T
A
A
2. C
3. Test points: V
Parameter
Parameter
2. Do not use the WAIT pin during CLKOUT asynchronous operation.
= −40 to +85°C, 2.7 V ≤ V
= −40 to +85°C, 1.8 V ≤ V
CLK
according to the setting of bits 4 and 5 (EW0, EW1) of the memory expansion mode control
register (MEM). When f
Use the separate bus mode during CLKOUT asynchronous operation.
L
: The pin load capacitance is 15 pF.
: CPU/peripheral hardware clock frequency
CHAPTER 29 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
OH
= 0.8V
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
CYK2
WRDL2
WWRL2
SRDDI2
HRDDI2
SWROD2
HKOD2
DRDA2
SWRA2
CYK2
WRDL2
WWRL2
SRDDI2
HRDDI2
SWROD2
HKOD2
DRDA2
SWRA2
DD
Symbol
Symbol
DD
DD
, V
CLK
= EV
= EV
OL
<18> 2.7 V ≤ V
<19> 2.7 V ≤ V
<20> 2.7 V ≤ V
<21> 2.7 V ≤ V
<22> 2.7 V ≤ V
<23> 2.7 V ≤ V
<24> 2.7 V ≤ V
<25> 2.7 V ≤ V
<26> 2.7 V ≤ V
<18>
<19>
<20>
<21>
<22>
<23>
<24>
<25>
<26>
User’s Manual U18432EJ5V0UD
is sufficiently high, insert a wait by setting the EW0 and EW1 bits.
= 0.2V
μ
DD0
DD0
PD78F117xA)
μ
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
2.7 V ≤ V
1.8 V ≤ V
= EV
= EV
PD78F117x)
DD
Conditions
Conditions
DD1
DD1
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
≤ 5.5 V, V
≤ 5.5 V, V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
≤ 5.5 V
< 2.7 V
SS
SS
1.8t
0.8t
1.8t
1.8t
0.8t
0.8t
= EV
= EV
t
t
t
t
t
CYK2
t
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
MIN.
MIN.
100
100
200
170
90
90
0
2
0
0
2
2
− 15
− 15
SS0
SS0
− 5
− 5
− 5
− 5
− 40
− 40
− 40
− 60
− 40
− 60
= EV
= EV
SS1
SS1
TYP.
TYP.
= AV
= AV
SS
SS
Standard Products
= 0 V)
= 0 V)
2.2t
1.2t
2.2t
2.2t
1.2t
1.2t
MAX.
MAX.
15
5
5
CYK2
CYK2
CYK2
CYK2
CYK2
CYK2
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns

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