UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 655

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
(2) DMA response time
The response time of DMA transfer is as follows.
Note
Response time
Cautions 1.
Remarks 1.
This is the time required to execute an instruction from internal ROM (without accessing data in
external memory). However, DMA transfers might be further delayed in the cases below. The
number of clock cycles by which transfers are delayed varies depending on the condition.
Executing an
instruction from
internal ROM
Executing an
instruction from
internal RAM
Executing an instruction from
external memory
3.
2.
2.
3.
Note
Do not specify successive transfer triggers for a channel within a period equal
to the maximum response time plus one clock cycle, because they might be
ignored.
Internal Wait : Number of clock cycles the system waits according to the clock
The above response time does not include the two clock cycles required for a
DMA transfer.
When executing a DMA pending instruction (see 16.6 (4)), the maximum
response time is extended by the execution time of that instruction to be held
pending.
External wait: Low level period of the WAIT pin of the external bus interface (in 1/f
1 clock: 1/f
Condition
Table 16-2. Response Time of DMA Transfer
When external memory
data is accessed
When external memory
data is not accessed
When external memory
data is accessed
CHAPTER 16 DMA CONTROLLER
CLK
User’s Manual U18432EJ5V0UD
(f
units). For details, see 5.6 Number of Instruction Wait Clocks for
External Wait Pin.
selected for the CLKOUT pin of the external bus interface
CLK
f
f
f
f
3 clocks
CLK
CLK
CLK
CLK
CLKOUT Pin Selection
: CPU clock)
/2
/3
/4
Minimum Time
Clock
8 + (3 × (external wait + internal wait)) clocks
16 clocks
16 + (3 × (external wait + internal wait)) clocks
16 + (12 × (external wait + internal wait)) clocks
Maximum Response Time
3 clocks
5 to 6 clocks
7 to 9 clocks
9 to 12 clocks
10 clocks
Number of Wait States
Maximum Time
653
CLK