UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 417

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 13-2 shows the block diagram of serial array unit 1.
(when CSI20: SCK20/
(when UART2: RxD2/
(when CSI21: SCK21/
(when UART3: RxD3/
(when IIC20: SDA20/
(when IIC21: SDA21/
(when IIC20: SCL20/
(when IIC21: SCL21/
Serial data input pin
P143/RxD2/SDA20)
Serial data input pin
(when CSI20: SI20/
Serial data input pin
P143/SI20/SDA20)
(when CSI21: SI21/
Serial clock I/O pin
Serial clock I/O pin
P143/RxD2/SI20)
When UART2
When UART3
P142/SCK20)
P126/SDA21)
P142/SCL20)
P125/SCK21)
P125/SCL21)
P126/SI21)
P14/EX28)
INTTM03
Peripheral enable
register 0 (PER0)
f
CLK
SAU1EN
SNFEN20
Channel 2 (LIN-bus supported)
Channel 3 (LIN-bus supported)
elimination
Channel 0
SNFEN30
enabled/
disabled
TXE
Channel 1
elimination
Noise
10
Selector
enabled/
disabled
Noise
PM142
RXE
PRS
10
113
detection
Edge
DAP
Edge/level
10
Edge/level
PRS
112
Edge/level
detection
detection
Serial clock select register 1 (SPS1)
detection
Serial communication operation setting register 10 (SCR10)
CK11
4
Figure 13-2. Block Diagram of Serial Array Unit 1
Output latch
CK11
Selector
CK11
CK11
CKP
0
(P142)
PRS
10
111
SCK
f
CLK
EOC
0
10
PRS
CK10
/2
110
Prescaler
0
to f
CK10
CHAPTER 13 SERIAL ARRAY UNIT
CK10
CK10
CLK
CKS10
PTC
0
101
PRS
103
/2
Serial mode register 10 (SMR10)
MCK
11
Selector
CCS10 STS10 MD102
User’s Manual U18432EJ5V0UD
PTC
100
0
PRS
102
(Clock division setting block)
4
f
f
CLK
CLK
DIR
1
10
PRS
101
/2
/2
0
11
to
SLC
101
1
PRS
100
Serial data register 10 (SDR10)
CKO11 CKO10
Serial output register 1 (SO1)
MD101
SLC
100
TCLK
DLS
102
(Buffer register block)
DLS
101
0
Shift register
Communication controller
Communication controller
Communication controller
Communication controller
(for transmission)
0
DLS
(for transmission)
100
Mode selection
Mode selection
Mode selection
CSI20 or IIC20
Mode selection
(for reception)
CSI21 or IIC21
(for reception)
or UART2
or UART2
UART3
UART3
0
TSF
10
Serial status register 10 (SSR10)
0
BFF
10
SE13 SE12 SE11
SS13 SS12 SS11
ST13
0
0
1
Serial flag clear trigger
register 10 (SIR10)
(P144 or p143)
Output latch
FECT
FEF
10
SOL12
SOE12 SOE11 SOE10
10
SO12 SO11
ST12 ST11
Error controller
Error controller
Error controller
controller
controller
PECT
Interrupt
PEF
10
Output
10
0
PM144 or PM143
OVCT
OVF
SOL10
10
10
SO10
ST10
SE10
SS10
information
Clear
Error
Serial channel enable
status register 1 (SE1)
Serial channel start
register 1 (SS1)
Serial channel stop
register 1 (ST1)
Serial output enable
register 1 (SOE1)
Serial output level
register 1 (SOL1)
Noise filter enable
register 0 (NFEN0)
SNFEN
30
Serial transfer end interrupt
(when CSI20: INTCSI20)
(when IIC20: INTIIC20)
(when UART2: INTST2)
Serial data output pin
(when CSI21: SO21/ P127)
(when IIC21: SDA21/
Serial transfer end interrupt
(when CSI21: INTCSI21)
(when IIC21: INTIIC21)
(when UART2: INTSR2)
Serial transfer error interrupt
(INTSRE2)
Serial transfer end interrupt
(when UART3: INTSR3)
Serial transfer error interrupt
(INTSRE3)
Serial data output pin
(when CSI20: SO20/
(when IIC20: SDA20/
(when UART2: TxD2/
Serial transfer end interrupt
(when UART3: INTST3)
Serial data output pin
(when UART3: TxD3/
SNFEN
20
P144/TxD2)
P143/SI20/RxD2)
P144/SO20)
P126/SI21)
P13/EX27)
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