UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 916

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

914
Memory
space
Processor
registers
Port
functions
Function
PMC: Processor
mode control
register
Internal data
memory space
SFR: Special
function register
area
2nd SFR:
Extended
special function
register
SP: Stack
pointer
General-purpose
registers
P01/TO00
P02/SO10/TxD1,
P03/SI10/RxD1/
SDA10,
P04/SCK10/
SCL10
P10/SCK00/
EX24,
P11/SI00/RxD0/
EX25,
P12/SO00/TxD0/
EX26,
P13/TxD3/EX27,
P14/RxD3/EX28
Details of
Function
Set PMC only once during the initial settings prior to operating the DMA controller.
Rewriting PMC other than during the initial settings is prohibited.
After setting PMC, wait for at least one instruction and access the mirror area.
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for
fetching instructions or as a stack area.
While using the self-programming function, the area of FFE20H to FFEFFH cannot
be used as a stack memory. Furthermore, the areas of F8700H to F8EFFH cannot
be used with the
Do not access addresses to which SFRs are not assigned.
Do not access addresses to which the 2nd SFR is not assigned.
Since reset signal generation makes the SP contents undefined, be sure to initialize
the SP before using the stack.
The values of the stack pointer must be set to even numbers. If odd numbers are
specified, the least significant bit is automatically cleared to 0.
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space as a
stack area.
While using the self-programming function, the area of FFE20H to FFEFFH cannot
be used as a stack memory. Furthermore, the areas of F8700H to F8EFFH cannot
be used with the
It is prohibited to use the general-purpose register (FFEE0H to FFEFFH) space for
fetching instructions or as a stack area.
To use P01/TO00 as a general-purpose port, set bit 0 (TO00) of timer output register
0 (TO0) and bit 0 (TOE00) of timer output enable register 0 (TOE0) to “0”, which is
the same as their default status setting.
To use P02/SO10/TxD1, P03/SI10/RxD1/SDA10, or P04/SCK10/SCL10 as a
general-purpose port, note the serial array unit 0 setting. For details, refer to the
following tables.
• Table 13-7 Relationship Between Register Settings and Pins (Channel 2 of Unit 0:
• Table 13-8 Relationship Between Register Settings and Pins (Channel 3 of Unit 0:
To
P13/TxD3/EX27, or P14/RxD3/EX28 as a general-purpose port, note the serial array
unit setting. For details, refer to the following tables.
• Table 13-5 Relationship Between Register Settings and Pins (Channel 0 of Unit 0:
• Table 13-6 Relationship Between Register Settings and Pins (Channel 1 of Unit 0:
• Table 13-11 Relationship Between Register Settings and Pins (Channel 2 of Unit 1:
• Table 13-12 Relationship Between Register Settings and Pins (Channel 3 of Unit 1:
CSI10, UART1 Transmission, IIC10)
CSI11, UART1 Reception, IIC11)
CSI00, UART0 Transmission)
CSI01, UART0 Reception)
UART3 Transmission)
UART3 Reception)
use
APPENDIX B LIST OF CAUTIONS
User’s Manual U18432EJ5V0UD
P10/SCK00/EX24,
μ
μ
PD78F1178 and
PD78F1178 and
μ
μ
P11/SI00/RxD0/EX25,
PD78F1178A, respectively.
PD78F1178A, respectively.
Cautions
P12/SO00/TxD0/EX26,
p.66
p.66
p.66
p.66
pp.67,
78
pp.67,
84
p.74
p.74
p.74
p.74
p.75
p.109
p.109
p.117
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