UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 193

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.7 Timing of External Bus Interface Function
(1) RD pin (alternate function: P64)
(2) WR0 pin (alternate function: P65)
(3) WR1 pin (alternate function: P66)
(4) WAIT pin (alternate function: P06)
(6) CLKOUT pin (alternate function: P05)
(7) EX0 to EX7, EX8 to EX15, EX16 to EX23, EX24 to EX31, and EX32 to EX35 pins (alternate function: P80 to
Figures 5-5 to 5-8 show the timing charts.
(5) ASTB pin (alternate function: P67)
The functions of the timing control signal output pins in the external memory extension mode are described below.
This pin outputs a read strobe signal when an instruction is fetched or data is read from the external memory.
It does not output the read strobe signal (holds the high level) when the internal memory is read.
This pin outputs a write strobe signal (in 8-bit bus mode or 16-bit bus mode (lower byte)) when data is written to
the external memory.
It does not output the write strobe signal (holds the high level) when data is written to the internal memory.
This pin outputs a write strobe signal (in 16-bit bus mode (higher byte)) when data is written to the external
memory.
It does not output the write strobe signal (holds the high level) when data is written to the internal memory.
This pin inputs an external wait signal.
A wait can be inserted to the bus cycle by inputting an external wait signal in synchronization with the CLKOUT
signal.
It can be used as an I/O port pin when the external wait signal is not used.
The external wait signal is ignored when the internal memory is accessed.
This pin outputs an address strobe signal.
This pin outputs the address strobe signal in the multiplexed bus mode.
During internal memory access, the address strobe signal is not output (the low level is maintained).
This pin outputs the internal system clock. The internal system clock is output when the external bus interface is
used (EXEN bit of the MEM register = 1).
P87, P50 to P57, P70 to P77, P10 to P17, and P90 to P93)
These pins output an address signal and input/output a data signal. A valid signal is output or input when an
instruction is fetched from or data is accessed to/from the external memory.
During internal memory access, the address output pin holds the address that was accessed last. The data
output pin goes into the Hi-Z state.
CHAPTER 5 EXTERNAL BUS INTERFACE
User’s Manual U18432EJ5V0UD
191