UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 303

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

7.7.4 Operation as input pulse interval measurement
measured.
clock.
same time, the counter (TCRmn) is cleared to 0000H, and the INTTMmn is output. If the counter overflows at this
time, the OVF bit of the TSRmn register is set to 1. If the counter does not overflow, the OVF bit is cleared. After that,
the above operation is repeated.
updated depending on whether the counter overflows during the measurement period. Therefore, the overflow status
of the captured value can be checked.
bit of the TSRmn register is set to 1. However, the OVF bit is configured as a cumulative flag, the correct interval
value cannot be measured if an overflow occurs more than once.
capture trigger.
The count value can be captured at the TImn valid edge and the interval of the pulse input to TImn can be
The pulse interval can be calculated by the following expression.
TCRmn operates as an up counter in the capture mode.
When the channel start trigger (TSmn) is set to 1, TCRmn counts up from 0000H in synchronization with the count
When the TImn pin input valid edge is detected, the count value is transferred (captured) to TDRmn and, at the
As soon as the count value has been captured to the TDRmn register, the OVF bit of the TSRmn register is
If the counter reaches a full count for two or more periods, it is judged to be an overflow occurrence, and the OVF
Set STSmn2 to STSmn0 of the TMRmn register to 001B to use the valid edges of TImn as a start trigger and a
When TEmn = 1, instead of the TImn pin input, a software operation (TSmn = 1) can be used as a capture trigger.
Operation
Remark
TImn pin
TImn input pulse interval = Period of count clock × ((10000H × TSRmn: OVF) + (Capture value of TDRmn + 1))
Caution The TImn pin input is sampled using the operating clock selected with the CKSmn bit of the
clock
TSmn
CKm1
CKm0
Figure 7-49. Block Diagram of Operation as Input Pulse Interval Measurement
TMRmn register, so an error equal to the number of operating clocks occurs.
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 7),
mn = 00 to 07, 10 to 13
detection
Edge
CHAPTER 7 TIMER ARRAY UNIT
User’s Manual U18432EJ5V0UD
Timer counter
Data register
(TCRmn)
(TDRmn)
controller
Interrupt
Interrupt signal
(INTTMmn)
301