UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 962

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

960
4th edition
Edition
Change of Cautions 3 and 5 in Figure 6-8 Format of Operation Speed Mode
Control Register (OSMC)
Change of Figure 6-13 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte:
LVIOFF = 1))
Change of Figure 6-14 Clock Generator Operation When Power Supply Voltage
Is Turned On (When LVI Default Start Function Enabled Is Set (Option Byte:
LVIOFF = 0)) and description of <1>
Change of 6.6.3 (1) <1> Setting P123/XT1 and P124/XT2 pins (CMC register)
Addition of description to 6.6.3 (3) <1> Confirming the CPU clock status (CKC
register)
Change of and deletion of Note in Figure 6-15 CPU Clock Status Transition
Diagram
Addition of Note to Table 6-5. Changing CPU Clock
Change of Table 6-6 Maximum Time Required for Main System Clock
Switchover
Change of channel number in 7.1.1 (4) Divider function
Change of Caution in Figure 7-5. Format of Peripheral Enable Register 0 (PER0)
Change of description of CCSmn bit in Figure 7-7 Format of Timer Mode Register
mn (TMRmn)
Change of Figure 7-21 Format of Timer Output Mode Register m (TOMm)
Change of description in 7.4.3 (1) Changing values set in registers TOm, TOEm,
TOLm, and TOMm during timer operation
Addition of description to 7.7.1 (1) Interval timer
Change of Figure 7-37 Block Diagram of Operation as Interval Timer/Square
Wave Output
Addition of (2) When f
Set Contents of Registers During Operation as Interval Timer/Square Wave
Output
Change of Figure 7-40 Operation Procedure of Interval Timer/Square Wave
Output Function
Change of description during operation in Figure 7-44 Operation Procedure When
External Event Counter Function Is Used
Change of channel number in 7.7.3 Operation as frequency divider
Change of description during operation in Figure 7-48 Operation Procedure When
Frequency Divider Function Is Used
Change of description during operation in Figure 7-52 Operation Procedure When
Input Pulse Interval Measurement Function Is Used
Change of description during operation in Figure 7-56 Operation Procedure When
Input Signal High-/Low-Level Width Measurement Function Is Used
Change of description during operation in Figure 7-61 Operation Procedure When
PWM Function Is Used
Change of description during operation in Figure 7-66 Operation Procedure of
One-Shot Pulse Output Function
Change of description during operation in Figure 7-71 Operation Procedure When
Multiple PWM Output Function Is Used
SUB
/4 is selected as count clock to Figure 7-39 Example of
APPENDIX C REVISION HISTORY
User’s Manual U18432EJ5V0UD
Description
CHAPTER 6 CLOCK
GENERATOR
CHAPTER 7 TIMER
ARRAY UNIT
Chapter
(8/13)