UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 487

• Manufacturer Part Number: UPD78F1174AGF-GAT-AX
• Description: MCU 16BIT 78K0R/KX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Kx3r

Specifications of UPD78F1174AGF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 16x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.5.6 Slave transmission/reception
transfer clock being input from another device.
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Clock phase
Data direction
Slave transmission/reception is that the 78K0R/KH3 transmits/receives data to/from another device in the state of a
Notes 1. Because the external serial clock input to pins SCK00, SCK01, SCK10, SCK11, SCK20, and SCK21 is
Remarks 1. f
3-Wire Serial I/O
2. Use this operation within a range that satisfies the conditions above and the AC characteristics in the
sampled internally and used, the fastest transfer rate is f
electrical specifications (see CHAPTER 29
PRODUCTS) and CHAPTER 30 ELECTRICAL SPECIFICATIONS ((A) GRADE PRODUCTS)).
2. m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
MCK
: Operation clock (MCK) frequency of target channel
Channel 0 of
SAU0
SCK00, SI00,
SO00
INTCSI00
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer mode)
can be selected.
Overrun error detection flag (OVFmn) only
7 or 8 bits
Max. f
Selectable by DAPmn bit
• DAPmn = 0: Data output starts from the start of the operation of the serial clock.
• DAPmn = 1: Data output starts half a clock before the start of the serial clock operation.
Selectable by CKPmn bit
• CKPmn = 0: Forward
• CKPmn = 1: Reverse
MSB or LSB first
CSI00
MCK
/6 [Hz]
Notes 1, 2
Channel 1 of
SAU0
SCK01, SI01,
SO01
INTCSI01
CHAPTER 13 SERIAL ARRAY UNIT
CSI01
User’s Manual U18432EJ5V0UD
Channel 2 of
SAU0
SCK10, SI10,
SO10
INTCSI10
CSI10
ELECTRICAL SPECIFICATIONS (STANDARD
MCK
Channel 3 of
SAU0
SCK11, SI11,
SO11
INTCSI11
/6 [Hz].
CSI11
Channel 0 of
SAU1
SCK20, SI20,
SO20
INTCSI20
CSI20
Channel 1 of
SAU1
SCK21, SI21,
SO21
INTCSI21
CSI21
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