UPD78F1174AGF-GAT-AX Renesas Electronics America, UPD78F1174AGF-GAT-AX Datasheet - Page 274

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UPD78F1174AGF-GAT-AX

Manufacturer Part Number
UPD78F1174AGF-GAT-AX
Description
MCU 16BIT 78K0R/KX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Kx3r
Datasheet

Specifications of UPD78F1174AGF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, EBI/EMI, I²C, LIN, UART/USART
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
111
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 16x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
UPD78F1174AGF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
<R>
<R>
272
Address: FFF3CH
(13) Input switch control register (ISC)
(14) Noise filter enable registers 1, 2 (NFEN1, NFEN2)
Symbol
ISC
Remark When the LIN-bus communication function is used, select the input signal of the RxD3 pin by setting
ISC is used to implement LIN-bus communication operation with channel 7 in association with serial array unit
1.
When bit 1 of this register is set to 1, the input signal of the serial data input pin (RxD3) is selected as a timer
input signal.
ISC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Caution Be sure to clear bits 7 to 2 to “0”.
NFEN1 and NFEN2 are used to set whether the noise filter can be used for the timer input signal to each
channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the
CPU/peripheral hardware clock (f
CPU/peripheral hardware clock (f
NFEN1 and NFEN2 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
ISC1
ISC0
ISC1 to 1 and setting TIS07 (bit 7 of the timer input select register 0 (TIS0)) to 0.
0
1
0
1
7
0
After reset: 00H
Uses the input signal of the TI07 pin as a timer input (normal operation).
Input signal of R
(to measure the pulse widths of the sync break field and sync field).
Uses the input signal of the INTP0 pin as an external interrupt (normal operation).
Uses the input signal of the R
Figure 7-22. Format of Input Switch Control Register (ISC)
6
0
R/W
CLK
CLK
X
CHAPTER 7 TIMER ARRAY UNIT
D3 pin is used as timer input (wakeup signal detection).
). When the noise filter is OFF, only synchronization is performed with the
).
5
0
User’s Manual U18432EJ5V0UD
Switching channel 7 input of timer array unit
X
Switching external interrupt (INTP0) input
D3 pin as an external interrupt (wakeup signal detection).
4
0
3
0
2
0
ISC1
1
ISC0
0

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